subject:"\[PATCH v2 2\/2\] pinctrl\: meson\-g12a\: add pinctrl driver support"

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

2018-07-16 Thread Yixun Lan



HI Jerome


On 07/16/18 17:54, Jerome Brunet wrote:
> 
 +/* uart_ao_a_ee */
 +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
 +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2 and c3 here.
>>>
>>
>> there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see
>>
>>  794 static const unsigned int uart_ao_tx_a_pins[]   = {
>> GPIOAO_0 };
>>  795 static const unsigned int uart_ao_rx_a_pins[]   = {
>> GPIOAO_1 };
>>
>> in the G12A ASIC design, some AO device (from function perspective)
>> route the pin to EE domain, for maximize pin mux utilization.
>>
>> if you don't like this naming scheme, I could rename it into
>>   uart_ao_rx_a_ee_pins[]
>>   uart_ao_tx_a_ee_pins[]
>>
> 
> What we are asking when requesting consistency is to respect a scheme.
> 
> 1) If the pin function is available only once:
> ${FUNCTION}_${PINFUNC}
> 2) If the pin function is available on the several banks
> ${FUNCTION}_${PINFUNC}_${BANK}
> 3)  If the pin function is available on the several pins of the same bank
> ${FUNCTION}_${PINfFUNC}_${BANK}${PINNUN}
> 

to be more accurate, I extend the syntax to

${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}

take " uart_ao_a_tx_c" as an example
FUNCTION = uart
DOMAIN= ao (may omit if it's belong to EE domain)
PORT=a (may omit if only one port)
PINFUNC = tx
BANK = C (may omit if only one BANK)
PINNUM = ? (only if two more same function in one BANK)


previous in AXG driver we follow scheme
${FUNCTION}_${DOMAIN}_${PINFUNC}_${PORT}_${BANK}${PINNUM}

which may bring confusion, since both PORT and BANK may use alphabet
character, it's hard to tell which is PORT or BANK at first glance.
even worse, sometimes either of PORT or BANK may be omitted..


> Either your function is uart_ao_a_ee and it is available only once then
> you should drop  c2 and c3
> 
> uart_ao_a_ee_rx and uart_ao_a_ee_tx
> 
> or the function is uart_ao_a which is available on ao and c bank then name
> should be 
> 
> uart_ao_a_rx_c, uart_ao_a_tx_c,
> 
we will take this way, has a note says it in the BANK-C sounds more
accurate,

> 
>> which mean uart_ao rx pin at port A route to EE domain's physical pin.
>>
> 
> [...]
> 
>>
 c const unsigned int pwm_f_h_pins[]= { GPIOH_5 };
 +
 +/* cec_ao_ee */
 +static const unsigned int cec_ao_a_ee_pins[]= { GPIOH_3 };
 +static const unsigned int cec_ao_b_ee_pins[]= { GPIOH_3 };
>>>
>>> Naming consistency : cec_ao_ee_a ? cec_ao_ee_b ?
>>>
>>
>> I'd prefer the original version, which mean cec_ao controller at port a
>> route to EE domain's physical pin.
>>
>> I would check this driver to see if there is inconsistency.
> 
> Then the function is CEC_AO not CEC_AO_EE.
> 
> Either the function is cec_ao_ee of cell A and B then name should be 
> 
> cec_ao_ee_a and cec_ao_ee_b
> 
> or function is cec_ao on bank H (also available on bank ao)
> 
> Then name should be cec_ao_a_h, cec_ao_b_h
> 
Ok, we will take this way


> Please choose.
> 
>>
>>
 +
 +/* jtag_b */
 +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
 +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
 +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
 +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
 +
 +/* bt565 */
 +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 };
 +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 };
 +static const unsigned int bt565_a_clk_pins[]= { GPIOZ_3 };
 +static const unsigned int bt565_a_din0_pins[]   = { GPIOZ_4 };
 +static const unsigned int bt565_a_din1_pins[]   = { GPIOZ_5 };
 +static const unsigned int bt565_a_din2_pins[]   = { GPIOZ_6 };
 +static const unsigned int bt565_a_din3_pins[]   = { GPIOZ_7 };
 +static const unsigned int bt565_a_din4_pins[]   = { GPIOZ_8 };
 +static const unsigned int bt565_a_din5_pins[]   = { GPIOZ_9 };
 +static const unsigned int bt565_a_din6_pins[]   = { GPIOZ_10 
 };
 +static const unsigned int bt565_a_din7_pins[]   = { GPIOZ_11 
 };
>>>
>>> Why bt565_a and no bt565 only ?
>>>
>>
>> After talking to Xingyu, this naming is actually taken from the pin mux
>> documentation, it's BT565_A there.
>>
>> I'm not sure if you insist to drop the _a suffix, personally I'd just
>> leave it as it is, for better consistence with documentation.
> 
> Then function name should be bt565_a
> 
sure, will fix this
>>
>>
 +
 +/* tsin_a */
 +static const unsigned int tsin_a_valid_pins[]   = { GPIOX_2 };
 +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 };
 +static const unsigned int tsin_a_din0_pins[]= { GPIOX_0 };
 +s

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

2018-07-16 Thread Jerome Brunet



> > > +/* uart_ao_a_ee */
> > > +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
> > > +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
> > 
> > Same comment as Martin about naming consistency ... drop c2 and c3 here.
> > 
> 
> there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see
> 
>  794 static const unsigned int uart_ao_tx_a_pins[]   = {
> GPIOAO_0 };
>  795 static const unsigned int uart_ao_rx_a_pins[]   = {
> GPIOAO_1 };
> 
> in the G12A ASIC design, some AO device (from function perspective)
> route the pin to EE domain, for maximize pin mux utilization.
> 
> if you don't like this naming scheme, I could rename it into
>   uart_ao_rx_a_ee_pins[]
>   uart_ao_tx_a_ee_pins[]
> 

What we are asking when requesting consistency is to respect a scheme.

1) If the pin function is available only once:
${FUNCTION}_${PINFUNC}
2) If the pin function is available on the several banks
${FUNCTION}_${PINFUNC}_${BANK}
3)  If the pin function is available on the several pins of the same bank
${FUNCTION}_${PINfFUNC}_${BANK}${PINNUN}

Either your function is uart_ao_a_ee and it is available only once then
you should drop  c2 and c3

uart_ao_a_ee_rx and uart_ao_a_ee_tx

or the function is uart_ao_a which is available on ao and c bank then name
should be 

uart_ao_a_rx_c, uart_ao_a_tx_c,


> which mean uart_ao rx pin at port A route to EE domain's physical pin.
> 

[...]

> 
> > > c const unsigned int pwm_f_h_pins[]= { GPIOH_5 };
> > > +
> > > +/* cec_ao_ee */
> > > +static const unsigned int cec_ao_a_ee_pins[]= { GPIOH_3 
> > > };
> > > +static const unsigned int cec_ao_b_ee_pins[]= { GPIOH_3 
> > > };
> > 
> > Naming consistency : cec_ao_ee_a ? cec_ao_ee_b ?
> > 
> 
> I'd prefer the original version, which mean cec_ao controller at port a
> route to EE domain's physical pin.
> 
> I would check this driver to see if there is inconsistency.

Then the function is CEC_AO not CEC_AO_EE.

Either the function is cec_ao_ee of cell A and B then name should be 

cec_ao_ee_a and cec_ao_ee_b

or function is cec_ao on bank H (also available on bank ao)

Then name should be cec_ao_a_h, cec_ao_b_h

Please choose.

> 
> 
> > > +
> > > +/* jtag_b */
> > > +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
> > > +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
> > > +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
> > > +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
> > > +
> > > +/* bt565 */
> > > +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 };
> > > +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 };
> > > +static const unsigned int bt565_a_clk_pins[]= { GPIOZ_3 
> > > };
> > > +static const unsigned int bt565_a_din0_pins[]   = { GPIOZ_4 
> > > };
> > > +static const unsigned int bt565_a_din1_pins[]   = { GPIOZ_5 
> > > };
> > > +static const unsigned int bt565_a_din2_pins[]   = { GPIOZ_6 
> > > };
> > > +static const unsigned int bt565_a_din3_pins[]   = { GPIOZ_7 
> > > };
> > > +static const unsigned int bt565_a_din4_pins[]   = { GPIOZ_8 
> > > };
> > > +static const unsigned int bt565_a_din5_pins[]   = { GPIOZ_9 
> > > };
> > > +static const unsigned int bt565_a_din6_pins[]   = { GPIOZ_10 
> > > };
> > > +static const unsigned int bt565_a_din7_pins[]   = { GPIOZ_11 
> > > };
> > 
> > Why bt565_a and no bt565 only ?
> > 
> 
> After talking to Xingyu, this naming is actually taken from the pin mux
> documentation, it's BT565_A there.
> 
> I'm not sure if you insist to drop the _a suffix, personally I'd just
> leave it as it is, for better consistence with documentation.

Then function name should be bt565_a

> 
> 
> > > +
> > > +/* tsin_a */
> > > +static const unsigned int tsin_a_valid_pins[]   = { GPIOX_2 
> > > };
> > > +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 };
> > > +static const unsigned int tsin_a_din0_pins[]= { GPIOX_0 
> > > };
> > > +static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 };
> > > +
> > > +/* tsin_b */
> > > +static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 
> > > };
> > > +static const unsigned int tsin_b_sop_x_pins[]   = { GPIOX_8 
> > > };
> > > +static const unsigned int tsin_b_din0_x_pins[]  = { GPIOX_10 
> > > };
> > > +static const unsigned int tsin_b_clk_x_pins[]   = { GPIOX_11 
> > > };
> > > +
> > > +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 
> > > };
> > > +static const unsigned int tsin_b_sop_z_pins[]   = { GPIOZ_3 
> > > };
> > > +static const unsigned int tsin_b_din0_z_pins[]  = { GPIOZ_4 
> > > };
> > > +static const unsigned int tsin_b_clk_z_pins[]   = { GPIOZ_5 
> > >

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

2018-07-16 Thread Yixun Lan

Hi Jerome

thanks for the review, see my comments below

On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>> Starting from Meson-AXG SoC, the pinctrl controller block use 4
>> continues register bits to specific the pin mux function, while comparing
>> to old generation SoC which using variable length register bits for
>> the pin mux definition. The new design greatly simplify the software model.
>>
>> For the detail example, one 32bit register can be divided into 8 parts,
>> each has 4 bits whose value start from 0 - 7, each can describe one pin,
>> the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
>> the mux pin function.
>>
>> Please note, the GPIOE is actually located at AO (always on) bank.
>>
>> Acked-by: Martin Blumenstingl 
>> Signed-off-by: Xingyu Chen 
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/pinctrl/meson/Kconfig  |6 +
>>  drivers/pinctrl/meson/Makefile |1 +
>>  drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
>>  3 files changed, 1440 insertions(+)
>>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
>>
>> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
>> index c80951d6caff..9ab537eb78a3 100644
>> --- a/drivers/pinctrl/meson/Kconfig
>> +++ b/drivers/pinctrl/meson/Kconfig
>> @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
>>  config PINCTRL_MESON_AXG_PMX
>>  bool
>>  
>> +config PINCTRL_MESON_G12A
>> +bool "Meson g12a Soc pinctrl driver"
>> +depends on ARM64
>> +select PINCTRL_MESON_AXG_PMX
>> +default y
>> +
>>  endif
>> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
>> index 3c6580c2d9d7..cf283f48f9d8 100644
>> --- a/drivers/pinctrl/meson/Makefile
>> +++ b/drivers/pinctrl/meson/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
>>  obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
>> +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
>> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
>> b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> new file mode 100644
>> index ..ca5cec40ac34
>> --- /dev/null
>> +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> @@ -0,0 +1,1433 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
>> +#include "pinctrl-meson.h"
>> +#include "pinctrl-meson-axg-pmx.h"
>> +
>>
> 
> [...]
> 
>> +/* uart_ao_a_ee */
>> +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
>> +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
> 
> Same comment as Martin about naming consistency ... drop c2 and c3 here.
> 

there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see

 794 static const unsigned int uart_ao_tx_a_pins[]   = {
GPIOAO_0 };
 795 static const unsigned int uart_ao_rx_a_pins[]   = {
GPIOAO_1 };

in the G12A ASIC design, some AO device (from function perspective)
route the pin to EE domain, for maximize pin mux utilization.

if you don't like this naming scheme, I could rename it into
  uart_ao_rx_a_ee_pins[]
  uart_ao_tx_a_ee_pins[]

which mean uart_ao rx pin at port A route to EE domain's physical pin.


>> +
>> +/* iso7816 */
>> +static const unsigned int iso7816_clk_c_pins[]  = { GPIOC_5 };
>> +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
>> +
>> +static const unsigned int iso7816_clk_x_pins[]  = { GPIOX_8 };
>> +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 };
>> +
>> +static const unsigned int iso7816_clk_h_pins[]  = { GPIOH_6 };
>> +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 };
>> +
>> +static const unsigned int iso7816_clk_z_pins[]  = { GPIOZ_0 };
>> +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 };
>> +
>> +/* eth */
>> +static const unsigned int eth_mdio_pins[]   = { GPIOZ_0 };
>> +static const unsigned int eth_mdc_pins[]= { GPIOZ_1 };
>> +static const unsigned int eth_rgmii_rx_clk_pins[]   = { GPIOZ_2 };
>> +static const unsigned int eth_rx_dv_pins[]  = { GPIOZ_3 };
>> +static const unsigned int eth_rxd0_pins[]   = { GPIOZ_4 };
>> +static const unsigned int eth_rxd1_pins[]   = { GPIOZ_5 };
>> +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 };
>> +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 };
>> +static const unsigned int eth_rgmii_tx_clk_p

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

2018-07-15 Thread Jerome Brunet

On Sat, 2018-07-14 at 23:27 +, Yixun Lan wrote:
> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
> the previous Meson-AXG SoC.
> 
> Starting from Meson-AXG SoC, the pinctrl controller block use 4
> continues register bits to specific the pin mux function, while comparing
> to old generation SoC which using variable length register bits for
> the pin mux definition. The new design greatly simplify the software model.
> 
> For the detail example, one 32bit register can be divided into 8 parts,
> each has 4 bits whose value start from 0 - 7, each can describe one pin,
> the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
> the mux pin function.
> 
> Please note, the GPIOE is actually located at AO (always on) bank.
> 
> Acked-by: Martin Blumenstingl 
> Signed-off-by: Xingyu Chen 
> Signed-off-by: Yixun Lan 
> ---
>  drivers/pinctrl/meson/Kconfig  |6 +
>  drivers/pinctrl/meson/Makefile |1 +
>  drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
>  3 files changed, 1440 insertions(+)
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
> 
> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
> index c80951d6caff..9ab537eb78a3 100644
> --- a/drivers/pinctrl/meson/Kconfig
> +++ b/drivers/pinctrl/meson/Kconfig
> @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
>  config PINCTRL_MESON_AXG_PMX
>   bool
>  
> +config PINCTRL_MESON_G12A
> + bool "Meson g12a Soc pinctrl driver"
> + depends on ARM64
> + select PINCTRL_MESON_AXG_PMX
> + default y
> +
>  endif
> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
> index 3c6580c2d9d7..cf283f48f9d8 100644
> --- a/drivers/pinctrl/meson/Makefile
> +++ b/drivers/pinctrl/meson/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
>  obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
>  obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
>  obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
> +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
> b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
> new file mode 100644
> index ..ca5cec40ac34
> --- /dev/null
> +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
> @@ -0,0 +1,1433 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
> + *
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + * Author: Xingyu Chen 
> + * Author: Yixun Lan 
> + */
> +
> +#include 
> +#include "pinctrl-meson.h"
> +#include "pinctrl-meson-axg-pmx.h"
> +
> 

[...]

> +/* uart_ao_a_ee */
> +static const unsigned int uart_ao_rx_a_c2_pins[] = { GPIOC_2 };
> +static const unsigned int uart_ao_tx_a_c3_pins[] = { GPIOC_3 };

Same comment as Martin about naming consistency ... drop c2 and c3 here.

> +
> +/* iso7816 */
> +static const unsigned int iso7816_clk_c_pins[]   = { GPIOC_5 };
> +static const unsigned int iso7816_data_c_pins[]  = { GPIOC_6 };
> +
> +static const unsigned int iso7816_clk_x_pins[]   = { GPIOX_8 };
> +static const unsigned int iso7816_data_x_pins[]  = { GPIOX_9 };
> +
> +static const unsigned int iso7816_clk_h_pins[]   = { GPIOH_6 };
> +static const unsigned int iso7816_data_h_pins[]  = { GPIOH_7 };
> +
> +static const unsigned int iso7816_clk_z_pins[]   = { GPIOZ_0 };
> +static const unsigned int iso7816_data_z_pins[]  = { GPIOZ_1 };
> +
> +/* eth */
> +static const unsigned int eth_mdio_pins[]= { GPIOZ_0 };
> +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
> +static const unsigned int eth_rgmii_rx_clk_pins[]= { GPIOZ_2 };
> +static const unsigned int eth_rx_dv_pins[]   = { GPIOZ_3 };
> +static const unsigned int eth_rxd0_pins[]= { GPIOZ_4 };
> +static const unsigned int eth_rxd1_pins[]= { GPIOZ_5 };
> +static const unsigned int eth_rxd2_rgmii_pins[]  = { GPIOZ_6 };
> +static const unsigned int eth_rxd3_rgmii_pins[]  = { GPIOZ_7 };
> +static const unsigned int eth_rgmii_tx_clk_pins[]= { GPIOZ_8 };
> +static const unsigned int eth_txen_pins[]= { GPIOZ_9 };
> +static const unsigned int eth_txd0_pins[]= { GPIOZ_10 };
> +static const unsigned int eth_txd1_pins[]= { GPIOZ_11 };
> +static const unsigned int eth_txd2_rgmii_pins[]  = { GPIOZ_12 };
> +static const unsigned int eth_txd3_rgmii_pins[]  = { GPIOZ_13 };
> +static const unsigned int eth_link_led_pins[]= { GPIOZ_14 };
> +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
> +
> +/* pwm_a */
> +static const unsigned int pwm_a_pins[]   = { GPIOX_6 };
> +
> +/* pwm_b */
> +static const unsigned int pwm_b_x7_pins[]

[PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

2018-07-14 Thread Yixun Lan

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/Kconfig  |6 +
 drivers/pinctrl/meson/Makefile |1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
 3 files changed, 1440 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index c80951d6caff..9ab537eb78a3 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
 config PINCTRL_MESON_AXG_PMX
bool
 
+config PINCTRL_MESON_G12A
+   bool "Meson g12a Soc pinctrl driver"
+   depends on ARM64
+   select PINCTRL_MESON_AXG_PMX
+   default y
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 3c6580c2d9d7..cf283f48f9d8 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
 obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
+obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
new file mode 100644
index ..ca5cec40ac34
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -0,0 +1,1433 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = {
+   MESON_PIN(GPIOZ_0),
+   MESON_PIN(GPIOZ_1),
+   MESON_PIN(GPIOZ_2),
+   MESON_PIN(GPIOZ_3),
+   MESON_PIN(GPIOZ_4),
+   MESON_PIN(GPIOZ_5),
+   MESON_PIN(GPIOZ_6),
+   MESON_PIN(GPIOZ_7),
+   MESON_PIN(GPIOZ_8),
+   MESON_PIN(GPIOZ_9),
+   MESON_PIN(GPIOZ_10),
+   MESON_PIN(GPIOZ_11),
+   MESON_PIN(GPIOZ_12),
+   MESON_PIN(GPIOZ_13),
+   MESON_PIN(GPIOZ_14),
+   MESON_PIN(GPIOZ_15),
+   MESON_PIN(GPIOH_0),
+   MESON_PIN(GPIOH_1),
+   MESON_PIN(GPIOH_2),
+   MESON_PIN(GPIOH_3),
+   MESON_PIN(GPIOH_4),
+   MESON_PIN(GPIOH_5),
+   MESON_PIN(GPIOH_6),
+   MESON_PIN(GPIOH_7),
+   MESON_PIN(GPIOH_8),
+   MESON_PIN(BOOT_0),
+   MESON_PIN(BOOT_1),
+   MESON_PIN(BOOT_2),
+   MESON_PIN(BOOT_3),
+   MESON_PIN(BOOT_4),
+   MESON_PIN(BOOT_5),
+   MESON_PIN(BOOT_6),
+   MESON_PIN(BOOT_7),
+   MESON_PIN(BOOT_8),
+   MESON_PIN(BOOT_9),
+   MESON_PIN(BOOT_10),
+   MESON_PIN(BOOT_11),
+   MESON_PIN(BOOT_12),
+   MESON_PIN(BOOT_13),
+   MESON_PIN(BOOT_14),
+   MESON_PIN(BOOT_15),
+   MESON_PIN(GPIOC_0),
+   MESON_PIN(GPIOC_1),
+   MESON_PIN(GPIOC_2),
+   MESON_PIN(GPIOC_3),
+   MESON_PIN(GPIOC_4),
+   MESON_PIN(GPIOC_5),
+   MESON_PIN(GPIOC_6),
+   MESON_PIN(GPIOC_7),
+   MESON_PIN(GPIOA_0),
+   MESON_PIN(GPIOA_1),
+   MESON_PIN(GPIOA_2),
+   MESON_PIN(GPIOA_3),
+   MESON_PIN(GPIOA_4),
+   MESON_PIN(GPIOA_5),
+   MESON_PIN(GPIOA_6),
+   MESON_PIN(GPIOA_7),
+   MESON_PIN(GPIOA_8),
+   MESON_PIN(GPIOA_9),
+   MESON_PIN(GPIOA_10),
+   MESON_PIN(GPIOA_11),
+   MESON_PIN(GPIOA_12),
+   MESON_PIN(GPIOA_13),
+   MESON_PIN(GPIOA_14),
+   MESON_PIN(GPIOA_15),
+   MESON_PIN(GPIOX_0),
+   MESON_PIN(GPIOX_1),
+   MESON_PIN(GPIOX_2),
+   MESON_PIN(GPIOX_3),
+   MESON_PIN(GPIOX_4),
+   MESON_PIN(GPIOX_5),
+   MESON_PIN(GPIOX_6),
+   MESON_PIN(GPIOX_7),
+   MESON_PIN(GPIOX_8),
+   MESON_PIN(GPIOX_9),
+   MESON_PIN(GPIOX_10),
+   MESON_PIN(GPIOX_11),
+   MESON_PIN(GPIOX_12),
+   MESON_PIN(GPIOX_13),
+   MESON_PIN(GPIOX_14),
+   MESON_PIN(GPIOX_15),
+   MESON_PIN(GPIOX_16),
+   MESON_PIN(GPIOX_17),
+   MESON_PIN(GPIOX_18),
+   MESON_PIN(GPIOX_19),

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

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