Re: [PATCH v2 2/2] pinctrl: qcom: Add sdm845 pinctrl driver

[Linus Walleij]

On Thu, Jan 11, 2018 at 7:00 AM, Bjorn Andersson
 wrote:

> From: Kyle Yan 
>
> This adds the pinctrl definitions for the TLMM of SDM845.
>
> Signed-off-by: Kyle Yan 
> Signed-off-by: Rajendra Nayak 
> Signed-off-by: Bjorn Andersson 

Patch applied for v4.17.

> Changes since v1:
> - Corrected the authorship of the patch
> - Updated pin list to v2 hardware

Does that mean the v1 hardware is some prototype, only existing inside
Qualcomm & associates, all of which needs to be trashed now?

I hope it doesn't mean "oh yeah we shipped a few
million phones with that but they need to have a different kernel
and will never work with upstream".

Yours,
Linus Walleij

Re: [PATCH v2 2/2] pinctrl: qcom: Add sdm845 pinctrl driver

[Linus Walleij]

On Thu, Jan 11, 2018 at 7:00 AM, Bjorn Andersson
 wrote:

> From: Kyle Yan 
>
> This adds the pinctrl definitions for the TLMM of SDM845.
>
> Signed-off-by: Kyle Yan 
> Signed-off-by: Rajendra Nayak 
> Signed-off-by: Bjorn Andersson 

Patch applied for v4.17.

> Changes since v1:
> - Corrected the authorship of the patch
> - Updated pin list to v2 hardware

Does that mean the v1 hardware is some prototype, only existing inside
Qualcomm & associates, all of which needs to be trashed now?

I hope it doesn't mean "oh yeah we shipped a few
million phones with that but they need to have a different kernel
and will never work with upstream".

Yours,
Linus Walleij

[PATCH v2 2/2] pinctrl: qcom: Add sdm845 pinctrl driver

[Bjorn Andersson]

From: Kyle Yan 

This adds the pinctrl definitions for the TLMM of SDM845.

Signed-off-by: Kyle Yan 
Signed-off-by: Rajendra Nayak 
Signed-off-by: Bjorn Andersson 
---

Changes since v1:
- Corrected the authorship of the patch
- Updated pin list to v2 hardware

 drivers/pinctrl/qcom/Kconfig  |9 +
 drivers/pinctrl/qcom/Makefile |1 +
 drivers/pinctrl/qcom/pinctrl-sdm845.c | 1323 +
 3 files changed, 1333 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm845.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 9e504dbc7fb5..684e100ddbbb 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -139,4 +139,13 @@ config PINCTRL_QCOM_SSBI_PMIC
  which are using SSBI for communication with SoC. Example PMIC's
  devices are pm8058 and pm8921.
 
+config PINCTRL_SDM845
+   tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
+   depends on GPIOLIB && OF
+   select PINCTRL_MSM
+   help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SDM845 platform.
+
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06c8b2ace05f..4f72f5c00ae0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
+obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c 
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
new file mode 100644
index ..2ab7a8885757
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -0,0 +1,1323 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)\
+   [msm_mux_##fname] = {   \
+   .name = #fname, \
+   .groups = fname##_groups,   \
+   .ngroups = ARRAY_SIZE(fname##_groups),  \
+   }
+
+#define NORTH  0x0050
+#define SOUTH  0x0090
+#define EAST   0x0010
+#define REG_SIZE 0x1000
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10)\
+   {   \
+   .name = "gpio" #id, \
+   .pins = gpio##id##_pins,\
+   .npins = ARRAY_SIZE(gpio##id##_pins),   \
+   .funcs = (int[]){   \
+   msm_mux_gpio, /* gpio mode */   \
+   msm_mux_##f1,   \
+   msm_mux_##f2,   \
+   msm_mux_##f3,   \
+   msm_mux_##f4,   \
+   msm_mux_##f5,   \
+   msm_mux_##f6,   \
+   msm_mux_##f7,   \
+   msm_mux_##f8,   \
+   msm_mux_##f9,   \
+   msm_mux_##f10   \
+   },  \
+   .nfuncs = 11,   \
+   .ctl_reg = base + REG_SIZE * id,\
+   .io_reg = base + 0x4 + REG_SIZE * id,   \
+   .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+   .intr_status_reg = base + 0xc + REG_SIZE * id,  \
+   .intr_target_reg = base + 0x8 + REG_SIZE * id,  \
+   .mux_bit = 2,   \
+   .pull_bit = 0,  \
+   .drv_bit = 6,   \
+   .oe_bit = 9,\
+   .in_bit = 0,\
+   .out_bit = 1,   \
+   .intr_enable_bit = 0,   \
+   .intr_status_bit = 0,   \
+   .intr_target_bit = 5,   \
+   .intr_target_kpss_val = 3,  \
+   .intr_raw_status_bit = 4,   \
+   .intr_polarity_bit = 1, \
+   .intr_detection_bit = 2,\
+   .intr_detection_width = 2,  \
+   }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+   {   \
+   .name = #pg_name, 

[PATCH v2 2/2] pinctrl: qcom: Add sdm845 pinctrl driver

[Bjorn Andersson]

From: Kyle Yan 

This adds the pinctrl definitions for the TLMM of SDM845.

Signed-off-by: Kyle Yan 
Signed-off-by: Rajendra Nayak 
Signed-off-by: Bjorn Andersson 
---

Changes since v1:
- Corrected the authorship of the patch
- Updated pin list to v2 hardware

 drivers/pinctrl/qcom/Kconfig  |9 +
 drivers/pinctrl/qcom/Makefile |1 +
 drivers/pinctrl/qcom/pinctrl-sdm845.c | 1323 +
 3 files changed, 1333 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm845.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 9e504dbc7fb5..684e100ddbbb 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -139,4 +139,13 @@ config PINCTRL_QCOM_SSBI_PMIC
  which are using SSBI for communication with SoC. Example PMIC's
  devices are pm8058 and pm8921.
 
+config PINCTRL_SDM845
+   tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
+   depends on GPIOLIB && OF
+   select PINCTRL_MSM
+   help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SDM845 platform.
+
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06c8b2ace05f..4f72f5c00ae0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
+obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c 
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
new file mode 100644
index ..2ab7a8885757
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -0,0 +1,1323 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)\
+   [msm_mux_##fname] = {   \
+   .name = #fname, \
+   .groups = fname##_groups,   \
+   .ngroups = ARRAY_SIZE(fname##_groups),  \
+   }
+
+#define NORTH  0x0050
+#define SOUTH  0x0090
+#define EAST   0x0010
+#define REG_SIZE 0x1000
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10)\
+   {   \
+   .name = "gpio" #id, \
+   .pins = gpio##id##_pins,\
+   .npins = ARRAY_SIZE(gpio##id##_pins),   \
+   .funcs = (int[]){   \
+   msm_mux_gpio, /* gpio mode */   \
+   msm_mux_##f1,   \
+   msm_mux_##f2,   \
+   msm_mux_##f3,   \
+   msm_mux_##f4,   \
+   msm_mux_##f5,   \
+   msm_mux_##f6,   \
+   msm_mux_##f7,   \
+   msm_mux_##f8,   \
+   msm_mux_##f9,   \
+   msm_mux_##f10   \
+   },  \
+   .nfuncs = 11,   \
+   .ctl_reg = base + REG_SIZE * id,\
+   .io_reg = base + 0x4 + REG_SIZE * id,   \
+   .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+   .intr_status_reg = base + 0xc + REG_SIZE * id,  \
+   .intr_target_reg = base + 0x8 + REG_SIZE * id,  \
+   .mux_bit = 2,   \
+   .pull_bit = 0,  \
+   .drv_bit = 6,   \
+   .oe_bit = 9,\
+   .in_bit = 0,\
+   .out_bit = 1,   \
+   .intr_enable_bit = 0,   \
+   .intr_status_bit = 0,   \
+   .intr_target_bit = 5,   \
+   .intr_target_kpss_val = 3,  \
+   .intr_raw_status_bit = 4,   \
+   .intr_polarity_bit = 1, \
+   .intr_detection_bit = 2,\
+   .intr_detection_width = 2,  \
+   }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+   {   \
+   .name = #pg_name,   \
+   .pins = pg_name##_pins, \
+   .npins =