Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-15 Thread Mark Brown 
On Fri, Apr 15, 2016 at 11:59:55AM +0530, Purna Chandra Mandal wrote:
> On 04/14/2016 11:25 AM, Mark Brown wrote:
> > On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:

> >> +  enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
> >> +  status = readl(sqi->regs + PESQI_INT_STAT_REG);
> >> +  if (!status)
> >> +  return IRQ_NONE;

> > For robustness the check should be if there was anything handled, not if
> > there was anything set.

> In PESQI controller INT_STAT_REG specifies interrupting reason(s) as usual,
> but mostly to confirm completion of on-going DMA operation. It is sticky,
> no way to acknowledge the interrupt source except masking the source.
> In short, whole interrupt logic is mere extension of status polling logic.

> And in driver isr logic is completely depended on the INT_STAT_REG; if status
> is zero no handling can be done and is unexpected!

That's fine, if something goes wrong there's error handling in genirq
which will notice that the interrupt is screaming and disable it.


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-15 Thread Mark Brown 
On Fri, Apr 15, 2016 at 11:59:55AM +0530, Purna Chandra Mandal wrote:
> On 04/14/2016 11:25 AM, Mark Brown wrote:
> > On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:

> >> +  enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
> >> +  status = readl(sqi->regs + PESQI_INT_STAT_REG);
> >> +  if (!status)
> >> +  return IRQ_NONE;

> > For robustness the check should be if there was anything handled, not if
> > there was anything set.

> In PESQI controller INT_STAT_REG specifies interrupting reason(s) as usual,
> but mostly to confirm completion of on-going DMA operation. It is sticky,
> no way to acknowledge the interrupt source except masking the source.
> In short, whole interrupt logic is mere extension of status polling logic.

> And in driver isr logic is completely depended on the INT_STAT_REG; if status
> is zero no handling can be done and is unexpected!

That's fine, if something goes wrong there's error handling in genirq
which will notice that the interrupt is screaming and disable it.


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-15 Thread Purna Chandra Mandal 
On 04/14/2016 11:25 AM, Mark Brown wrote:

> On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:
>
>> +enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
>> +status = readl(sqi->regs + PESQI_INT_STAT_REG);
>> +if (!status)
>> +return IRQ_NONE;
>> +
> For robustness the check should be if there was anything handled, not if
> there was anything set.

In PESQI controller INT_STAT_REG specifies interrupting reason(s) as usual,
but mostly to confirm completion of on-going DMA operation. It is sticky,
no way to acknowledge the interrupt source except masking the source.
In short, whole interrupt logic is mere extension of status polling logic.

And in driver isr logic is completely depended on the INT_STAT_REG; if status
is zero no handling can be done and is unexpected!

>> +static dma_addr_t pic32_sqi_map_transfer(struct pic32_sqi *sqi,
>> + struct spi_transfer *transfer)
>> +{
>> +struct device *dev = >master->dev;
> Don't open code DMA mapping of the buffers, use the core support.

Make sense. Will use core support.

>> +reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +sqi->regs = devm_ioremap_resource(>dev, reg);
>> +if (!sqi->regs) {
>> +dev_err(>dev, "mem map failed\n");
> devm_ioremap_resource() will log for you.

ack.

>> +clk_prepare_enable(sqi->sys_clk);
>> +clk_prepare_enable(sqi->base_clk);
> Check the return value please.

Will add.

>> +/* install irq handlers */
>> +ret = devm_request_irq(>dev, sqi->irq, pic32_sqi_isr,
>> +   0, dev_name(>dev), sqi);
>> +if (ret < 0) {
>> +dev_err(>dev, "request-irq %d, failed ?\n", sqi->irq);
>> +goto err_free_ring;
>> +}
> This will free before the clocks are disabled.  Are you sure that's
> safe?  It's generally not good to mix devm_ and non-devm operations
> especially things like these that aren't simple frees of data.  It is
> safer to use a normal request_irq().

Yes, will use request_irq() instead.

>> +static int pic32_sqi_remove(struct platform_device *pdev)
>> +{
>> +struct pic32_sqi *sqi = platform_get_drvdata(pdev);
>> +
>> +clk_disable_unprepare(sqi->base_clk);
>> +clk_disable_unprepare(sqi->sys_clk);
>> +
>> +/* release memory */
>> +ring_desc_ring_free(sqi);
> This will free the descriptor ring before the interrupt...

ack, Will correct disable/free order.

Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-15 Thread Purna Chandra Mandal 
On 04/14/2016 11:25 AM, Mark Brown wrote:

> On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:
>
>> +enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
>> +status = readl(sqi->regs + PESQI_INT_STAT_REG);
>> +if (!status)
>> +return IRQ_NONE;
>> +
> For robustness the check should be if there was anything handled, not if
> there was anything set.

In PESQI controller INT_STAT_REG specifies interrupting reason(s) as usual,
but mostly to confirm completion of on-going DMA operation. It is sticky,
no way to acknowledge the interrupt source except masking the source.
In short, whole interrupt logic is mere extension of status polling logic.

And in driver isr logic is completely depended on the INT_STAT_REG; if status
is zero no handling can be done and is unexpected!

>> +static dma_addr_t pic32_sqi_map_transfer(struct pic32_sqi *sqi,
>> + struct spi_transfer *transfer)
>> +{
>> +struct device *dev = >master->dev;
> Don't open code DMA mapping of the buffers, use the core support.

Make sense. Will use core support.

>> +reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +sqi->regs = devm_ioremap_resource(>dev, reg);
>> +if (!sqi->regs) {
>> +dev_err(>dev, "mem map failed\n");
> devm_ioremap_resource() will log for you.

ack.

>> +clk_prepare_enable(sqi->sys_clk);
>> +clk_prepare_enable(sqi->base_clk);
> Check the return value please.

Will add.

>> +/* install irq handlers */
>> +ret = devm_request_irq(>dev, sqi->irq, pic32_sqi_isr,
>> +   0, dev_name(>dev), sqi);
>> +if (ret < 0) {
>> +dev_err(>dev, "request-irq %d, failed ?\n", sqi->irq);
>> +goto err_free_ring;
>> +}
> This will free before the clocks are disabled.  Are you sure that's
> safe?  It's generally not good to mix devm_ and non-devm operations
> especially things like these that aren't simple frees of data.  It is
> safer to use a normal request_irq().

Yes, will use request_irq() instead.

>> +static int pic32_sqi_remove(struct platform_device *pdev)
>> +{
>> +struct pic32_sqi *sqi = platform_get_drvdata(pdev);
>> +
>> +clk_disable_unprepare(sqi->base_clk);
>> +clk_disable_unprepare(sqi->sys_clk);
>> +
>> +/* release memory */
>> +ring_desc_ring_free(sqi);
> This will free the descriptor ring before the interrupt...

ack, Will correct disable/free order.

Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-13 Thread Mark Brown 
On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:

> + enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
> + status = readl(sqi->regs + PESQI_INT_STAT_REG);
> + if (!status)
> + return IRQ_NONE;
> +

For robustness the check should be if there was anything handled, not if
there was anything set.

> +static dma_addr_t pic32_sqi_map_transfer(struct pic32_sqi *sqi,
> +  struct spi_transfer *transfer)
> +{
> + struct device *dev = >master->dev;

Don't open code DMA mapping of the buffers, use the core support.

> + reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + sqi->regs = devm_ioremap_resource(>dev, reg);
> + if (!sqi->regs) {
> + dev_err(>dev, "mem map failed\n");

devm_ioremap_resource() will log for you.

> + clk_prepare_enable(sqi->sys_clk);
> + clk_prepare_enable(sqi->base_clk);

Check the return value please.

> + /* install irq handlers */
> + ret = devm_request_irq(>dev, sqi->irq, pic32_sqi_isr,
> +0, dev_name(>dev), sqi);
> + if (ret < 0) {
> + dev_err(>dev, "request-irq %d, failed ?\n", sqi->irq);
> + goto err_free_ring;
> + }

This will free before the clocks are disabled.  Are you sure that's
safe?  It's generally not good to mix devm_ and non-devm operations
especially things like these that aren't simple frees of data.  It is
safer to use a normal request_irq().

> +static int pic32_sqi_remove(struct platform_device *pdev)
> +{
> + struct pic32_sqi *sqi = platform_get_drvdata(pdev);
> +
> + clk_disable_unprepare(sqi->base_clk);
> + clk_disable_unprepare(sqi->sys_clk);
> +
> + /* release memory */
> + ring_desc_ring_free(sqi);

This will free the descriptor ring before the interrupt...


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-13 Thread Mark Brown 
On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:

> + enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
> + status = readl(sqi->regs + PESQI_INT_STAT_REG);
> + if (!status)
> + return IRQ_NONE;
> +

For robustness the check should be if there was anything handled, not if
there was anything set.

> +static dma_addr_t pic32_sqi_map_transfer(struct pic32_sqi *sqi,
> +  struct spi_transfer *transfer)
> +{
> + struct device *dev = >master->dev;

Don't open code DMA mapping of the buffers, use the core support.

> + reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + sqi->regs = devm_ioremap_resource(>dev, reg);
> + if (!sqi->regs) {
> + dev_err(>dev, "mem map failed\n");

devm_ioremap_resource() will log for you.

> + clk_prepare_enable(sqi->sys_clk);
> + clk_prepare_enable(sqi->base_clk);

Check the return value please.

> + /* install irq handlers */
> + ret = devm_request_irq(>dev, sqi->irq, pic32_sqi_isr,
> +0, dev_name(>dev), sqi);
> + if (ret < 0) {
> + dev_err(>dev, "request-irq %d, failed ?\n", sqi->irq);
> + goto err_free_ring;
> + }

This will free before the clocks are disabled.  Are you sure that's
safe?  It's generally not good to mix devm_ and non-devm operations
especially things like these that aren't simple frees of data.  It is
safer to use a normal request_irq().

> +static int pic32_sqi_remove(struct platform_device *pdev)
> +{
> + struct pic32_sqi *sqi = platform_get_drvdata(pdev);
> +
> + clk_disable_unprepare(sqi->base_clk);
> + clk_disable_unprepare(sqi->sys_clk);
> +
> + /* release memory */
> + ring_desc_ring_free(sqi);

This will free the descriptor ring before the interrupt...


signature.asc
Description: PGP signature

[PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-13 Thread Purna Chandra Mandal 
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.

Signed-off-by: Purna Chandra Mandal 
Cc: Mark Brown 

---

 drivers/spi/Kconfig |   6 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-pic32-sqi.c | 815 
 3 files changed, 822 insertions(+)
 create mode 100644 drivers/spi/spi-pic32-sqi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8a8ff50..281ed5d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -442,6 +442,12 @@ config SPI_PIC32
help
  SPI driver for Microchip PIC32 SPI master controller.
 
+config SPI_PIC32_SQI
+   tristate "Microchip PIC32 Quad SPI driver"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for PIC32 Quad SPI controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06019ed..3c74d00 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
 obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
+obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o spi-pxa2xx-dma.o
diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c
new file mode 100644
index 000..bb31dc8
--- /dev/null
+++ b/drivers/spi/spi-pic32-sqi.c
@@ -0,0 +1,815 @@
+/*
+ * PIC32 Quad SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SQI registers */
+#define PESQI_XIP_CONF1_REG0x00
+#define PESQI_XIP_CONF2_REG0x04
+#define PESQI_CONF_REG 0x08
+#define PESQI_CTRL_REG 0x0C
+#define PESQI_CLK_CTRL_REG 0x10
+#define PESQI_CMD_THRES_REG0x14
+#define PESQI_INT_THRES_REG0x18
+#define PESQI_INT_ENABLE_REG   0x1C
+#define PESQI_INT_STAT_REG 0x20
+#define PESQI_TX_DATA_REG  0x24
+#define PESQI_RX_DATA_REG  0x28
+#define PESQI_STAT1_REG0x2C
+#define PESQI_STAT2_REG0x30
+#define PESQI_BD_CTRL_REG  0x34
+#define PESQI_BD_CUR_ADDR_REG  0x38
+#define PESQI_BD_BASE_ADDR_REG 0x40
+#define PESQI_BD_STAT_REG  0x44
+#define PESQI_BD_POLL_CTRL_REG 0x48
+#define PESQI_BD_TX_DMA_STAT_REG   0x4C
+#define PESQI_BD_RX_DMA_STAT_REG   0x50
+#define PESQI_THRES_REG0x54
+#define PESQI_INT_SIGEN_REG0x58
+
+/* PESQI_CONF_REG fields */
+#define PESQI_MODE 0x7
+#define  PESQI_MODE_BOOT   0
+#define  PESQI_MODE_PIO1
+#define  PESQI_MODE_DMA2
+#define  PESQI_MODE_XIP3
+#define PESQI_MODE_SHIFT   0
+#define PESQI_CPHA BIT(3)
+#define PESQI_CPOL BIT(4)
+#define PESQI_LSBF BIT(5)
+#define PESQI_RXLATCH  BIT(7)
+#define PESQI_SERMODE  BIT(8)
+#define PESQI_WP_ENBIT(9)
+#define PESQI_HOLD_EN  BIT(10)
+#define PESQI_BURST_EN BIT(12)
+#define PESQI_CS_CTRL_HW   BIT(15)
+#define PESQI_SOFT_RESET   BIT(16)
+#define PESQI_LANES_SHIFT  20
+#define  PESQI_SINGLE_LANE 0
+#define  PESQI_DUAL_LANE   1
+#define  PESQI_QUAD_LANE   2
+#define PESQI_CSEN_SHIFT   24
+#define PESQI_EN   BIT(23)
+
+/* PESQI_CLK_CTRL_REG fields */
+#define PESQI_CLK_EN   BIT(0)
+#define PESQI_CLK_STABLE   BIT(1)
+#define PESQI_CLKDIV_SHIFT 8
+#define PESQI_CLKDIV   0xff
+
+/* PESQI_INT_THR/CMD_THR_REG */
+#define PESQI_TXTHR_MASK   0x1f
+#define PESQI_TXTHR_SHIFT  8
+#define PESQI_RXTHR_MASK   0x1f
+#define PESQI_RXTHR_SHIFT  0
+
+/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */
+#define PESQI_TXEMPTY  BIT(0)
+#define PESQI_TXFULL   BIT(1)
+#define PESQI_TXTHRBIT(2)
+#define PESQI_RXEMPTY  BIT(3)
+#define

[PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-13 Thread Purna Chandra Mandal 
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.

Signed-off-by: Purna Chandra Mandal 
Cc: Mark Brown 

---

 drivers/spi/Kconfig |   6 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-pic32-sqi.c | 815 
 3 files changed, 822 insertions(+)
 create mode 100644 drivers/spi/spi-pic32-sqi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8a8ff50..281ed5d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -442,6 +442,12 @@ config SPI_PIC32
help
  SPI driver for Microchip PIC32 SPI master controller.
 
+config SPI_PIC32_SQI
+   tristate "Microchip PIC32 Quad SPI driver"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for PIC32 Quad SPI controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06019ed..3c74d00 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
 obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
+obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o spi-pxa2xx-dma.o
diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c
new file mode 100644
index 000..bb31dc8
--- /dev/null
+++ b/drivers/spi/spi-pic32-sqi.c
@@ -0,0 +1,815 @@
+/*
+ * PIC32 Quad SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SQI registers */
+#define PESQI_XIP_CONF1_REG0x00
+#define PESQI_XIP_CONF2_REG0x04
+#define PESQI_CONF_REG 0x08
+#define PESQI_CTRL_REG 0x0C
+#define PESQI_CLK_CTRL_REG 0x10
+#define PESQI_CMD_THRES_REG0x14
+#define PESQI_INT_THRES_REG0x18
+#define PESQI_INT_ENABLE_REG   0x1C
+#define PESQI_INT_STAT_REG 0x20
+#define PESQI_TX_DATA_REG  0x24
+#define PESQI_RX_DATA_REG  0x28
+#define PESQI_STAT1_REG0x2C
+#define PESQI_STAT2_REG0x30
+#define PESQI_BD_CTRL_REG  0x34
+#define PESQI_BD_CUR_ADDR_REG  0x38
+#define PESQI_BD_BASE_ADDR_REG 0x40
+#define PESQI_BD_STAT_REG  0x44
+#define PESQI_BD_POLL_CTRL_REG 0x48
+#define PESQI_BD_TX_DMA_STAT_REG   0x4C
+#define PESQI_BD_RX_DMA_STAT_REG   0x50
+#define PESQI_THRES_REG0x54
+#define PESQI_INT_SIGEN_REG0x58
+
+/* PESQI_CONF_REG fields */
+#define PESQI_MODE 0x7
+#define  PESQI_MODE_BOOT   0
+#define  PESQI_MODE_PIO1
+#define  PESQI_MODE_DMA2
+#define  PESQI_MODE_XIP3
+#define PESQI_MODE_SHIFT   0
+#define PESQI_CPHA BIT(3)
+#define PESQI_CPOL BIT(4)
+#define PESQI_LSBF BIT(5)
+#define PESQI_RXLATCH  BIT(7)
+#define PESQI_SERMODE  BIT(8)
+#define PESQI_WP_ENBIT(9)
+#define PESQI_HOLD_EN  BIT(10)
+#define PESQI_BURST_EN BIT(12)
+#define PESQI_CS_CTRL_HW   BIT(15)
+#define PESQI_SOFT_RESET   BIT(16)
+#define PESQI_LANES_SHIFT  20
+#define  PESQI_SINGLE_LANE 0
+#define  PESQI_DUAL_LANE   1
+#define  PESQI_QUAD_LANE   2
+#define PESQI_CSEN_SHIFT   24
+#define PESQI_EN   BIT(23)
+
+/* PESQI_CLK_CTRL_REG fields */
+#define PESQI_CLK_EN   BIT(0)
+#define PESQI_CLK_STABLE   BIT(1)
+#define PESQI_CLKDIV_SHIFT 8
+#define PESQI_CLKDIV   0xff
+
+/* PESQI_INT_THR/CMD_THR_REG */
+#define PESQI_TXTHR_MASK   0x1f
+#define PESQI_TXTHR_SHIFT  8
+#define PESQI_RXTHR_MASK   0x1f
+#define PESQI_RXTHR_SHIFT  0
+
+/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */
+#define PESQI_TXEMPTY  BIT(0)
+#define PESQI_TXFULL   BIT(1)
+#define PESQI_TXTHRBIT(2)
+#define PESQI_RXEMPTY  BIT(3)
+#define PESQI_RXFULL   BIT(4)
+#define PESQI_RXTHRBIT(5)
+#define