Re: [PATCH v2 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
Quoting matthias@kernel.org (2018-11-16 10:09:01)
> From: Jasper Mattsson
>
> This marks MUXes axi_sel and ddrphycfg_sel as well as gates
> infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
>
> Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
> Signed-off-by: Jasper Mattsson
> Signed-off-by: Matthias Brugger
> ---
Can you add comments in the commit text and in the code about why the
CLK_IS_CRITICAL flag is added to these clks? It makes it easier to
figure out why the flag is there months from now when we all forget
Re: [PATCH v2 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
Quoting matthias@kernel.org (2018-11-16 10:09:01)
> From: Jasper Mattsson
>
> This marks MUXes axi_sel and ddrphycfg_sel as well as gates
> infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
>
> Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
> Signed-off-by: Jasper Mattsson
> Signed-off-by: Matthias Brugger
> ---
Can you add comments in the commit text and in the code about why the
CLK_IS_CRITICAL flag is added to these clks? It makes it easier to
figure out why the flag is there months from now when we all forget
[PATCH v2 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
From: Jasper Mattsson
This marks MUXes axi_sel and ddrphycfg_sel as well as gates
infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
Signed-off-by: Jasper Mattsson
Signed-off-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6797.c | 64 ++-
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6797.c
b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc974ed9..20b106764423 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -329,10 +329,10 @@ static const struct mtk_composite top_muxes[] = {
ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
- MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
- 0x0040, 0, 2),
- MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
- 0x0040, 16, 2),
+ MUX_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
+ 0x0040, 0, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
0x0040, 24, 2),
MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,31 +424,39 @@ static const struct mtk_gate_regs infra2_cg_regs = {
.sta_ofs = 0x00b0,
};
-#define GATE_ICG0(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = _cg_regs,\
- .shift = _shift,\
- .ops = _clk_gate_ops_setclr,\
+#define GATE_ICG0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _cg_regs,\
+ .shift = _shift,\
+ .ops = _clk_gate_ops_setclr,\
}
-#define GATE_ICG1(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = _cg_regs,\
- .shift = _shift,\
- .ops = _clk_gate_ops_setclr,\
+#define GATE_ICG1(_id, _name, _parent, _shift) \
+ GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _cg_regs,\
+ .shift = _shift,\
+ .ops = _clk_gate_ops_setclr,\
+ .flags = _flags,\
}
-#define GATE_ICG2(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = _cg_regs,\
- .shift = _shift,\
- .ops = _clk_gate_ops_setclr,\
+#define GATE_ICG2(_id, _name, _parent, _shift) \
+ GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _cg_regs,\
+ .shift = _shift,\
+ .ops = _clk_gate_ops_setclr,\
+ .flags = _flags,\
}
static const struct mtk_gate infra_clks[] = {
@@ -505,7 +513,8 @@ static const struct mtk_gate infra_clks[] = {
GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
- GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+ GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+
[PATCH v2 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
From: Jasper Mattsson
This marks MUXes axi_sel and ddrphycfg_sel as well as gates
infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
Signed-off-by: Jasper Mattsson
Signed-off-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6797.c | 64 ++-
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6797.c
b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc974ed9..20b106764423 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -329,10 +329,10 @@ static const struct mtk_composite top_muxes[] = {
ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
- MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
- 0x0040, 0, 2),
- MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
- 0x0040, 16, 2),
+ MUX_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
+ 0x0040, 0, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
0x0040, 24, 2),
MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,31 +424,39 @@ static const struct mtk_gate_regs infra2_cg_regs = {
.sta_ofs = 0x00b0,
};
-#define GATE_ICG0(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = _cg_regs,\
- .shift = _shift,\
- .ops = _clk_gate_ops_setclr,\
+#define GATE_ICG0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _cg_regs,\
+ .shift = _shift,\
+ .ops = _clk_gate_ops_setclr,\
}
-#define GATE_ICG1(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = _cg_regs,\
- .shift = _shift,\
- .ops = _clk_gate_ops_setclr,\
+#define GATE_ICG1(_id, _name, _parent, _shift) \
+ GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _cg_regs,\
+ .shift = _shift,\
+ .ops = _clk_gate_ops_setclr,\
+ .flags = _flags,\
}
-#define GATE_ICG2(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = _cg_regs,\
- .shift = _shift,\
- .ops = _clk_gate_ops_setclr,\
+#define GATE_ICG2(_id, _name, _parent, _shift) \
+ GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _cg_regs,\
+ .shift = _shift,\
+ .ops = _clk_gate_ops_setclr,\
+ .flags = _flags,\
}
static const struct mtk_gate infra_clks[] = {
@@ -505,7 +513,8 @@ static const struct mtk_gate infra_clks[] = {
GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
- GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+ GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+
