Re: [PATCH v2 3/5] arm64: dts: actions: Add gpio line names to Bubblegum-96 board

2018-05-23 Thread Linus Walleij 
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
 wrote:

> Add gpio line names to Actions Semi S900 based Bubblegum-96 board.
>
> Signed-off-by: Manivannan Sadhasivam 

Reviewed-by: Linus Walleij 

Yours,
Linus Walleij

Re: [PATCH v2 3/5] arm64: dts: actions: Add gpio line names to Bubblegum-96 board

2018-05-23 Thread Linus Walleij 
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
 wrote:

> Add gpio line names to Actions Semi S900 based Bubblegum-96 board.
>
> Signed-off-by: Manivannan Sadhasivam 

Reviewed-by: Linus Walleij 

Yours,
Linus Walleij

[PATCH v2 3/5] arm64: dts: actions: Add gpio line names to Bubblegum-96 board

2018-05-19 Thread Manivannan Sadhasivam 
Add gpio line names to Actions Semi S900 based Bubblegum-96 board.

Signed-off-by: Manivannan Sadhasivam 
---
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 175 ++
 1 file changed, 175 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts 
b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index ff043c961d75..d0ba35df9015 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -34,3 +34,178 @@
status = "okay";
clocks = < CLK_UART5>;
 };
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (pin out but not routed from the chip to
+ *  anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * LSEC = Low Speed External Connector
+ * HSEC = High Speed External Connector
+ *
+ * Line names are taken from the schematic "Schematics Bubblegum96"
+ * version v1.0
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Boards naming of a line and the schematic name of
+ * the same line are in conflict, the 96Boards specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART2. Only exception is the I2C lines for which the schematic
+ * naming has been preferred. This is only for the informational
+ * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
+ * are the only ones actually used for GPIO.
+ */
+
+ {
+   gpio-line-names =
+   "GPIO-A", /* GPIO_0, LSEC pin 23 */
+   "GPIO-B", /* GPIO_1, LSEC pin 24 */
+   "GPIO-C", /* GPIO_2, LSEC pin 25 */
+   "GPIO-D", /* GPIO_3, LSEC pin 26 */
+   "GPIO-E", /* GPIO_4, LSEC pin 27 */
+   "GPIO-F", /* GPIO_5, LSEC pin 28 */
+   "GPIO-G", /* GPIO_6, LSEC pin 29 */
+   "GPIO-H", /* GPIO_7, LSEC pin 30 */
+   "GPIO-I", /* GPIO_8, LSEC pin 31 */
+   "GPIO-J", /* GPIO_9, LSEC pin 32 */
+   "NC", /* GPIO_10 */
+   "NC", /* GPIO_11 */
+   "SIRQ2_1V8", /* GPIO_12 */
+   "PCM0_OUT", /* GPIO_13 */
+   "WIFI_LED", /* GPIO_14 */
+   "PCM0_SYNC", /* GPIO_15 */
+   "PCM0_CLK", /* GPIO_16 */
+   "PCM0_IN", /* GPIO_17 */
+   "BT_LED", /* GPIO_18 */
+   "LED0", /* GPIO_19 */
+   "LED1", /* GPIO_20 */
+   "JTAG_TCK", /* GPIO_21 */
+   "JTAG_TMS", /* GPIO_22 */
+   "JTAG_TDI", /* GPIO_23 */
+   "JTAG_TDO", /* GPIO_24 */
+   "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */
+   "NC", /* GPIO_26 */
+   "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */
+   "SD0_D0", /* GPIO_28 */
+   "SD0_D1", /* GPIO_29 */
+   "SD0_D2", /* GPIO_30 */
+   "SD0_D3", /* GPIO_31 */
+   "SD1_D0", /* GPIO_32 */
+   "SD1_D1", /* GPIO_33 */
+   "SD1_D2", /* GPIO_34 */
+   "SD1_D3", /* GPIO_35 */
+   "SD0_CMD", /* GPIO_36 */
+   "SD0_CLK", /* GPIO_37 */
+   "SD1_CMD", /* GPIO_38 */
+   "SD1_CLK", /* GPIO_39 */
+   "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */
+   "SPI0_CS", /* GPIO_41, LSEC pin 12 */
+   "SPI0_DIN", /* GPIO_42, LSEC pin 10 */
+   "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */
+   "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */
+   "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */
+   "UART0_RX", /* GPIO_46, LSEC pin 7 */
+   "UART0_TX", /* GPIO_47, LSEC pin 5 */
+   "UART0_RTSB", /* GPIO_48, LSEC pin 9 */
+   "UART0_CTSB", /* GPIO_49, LSEC pin 3 */
+   "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */
+   "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */
+   "I2C0_SCLK", /* GPIO_52 */
+   "I2C0_SDATA", /* GPIO_53 */
+   "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */
+   "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */
+   "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */
+   "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */
+   "CSI0_DN0", /* GPIO_58, HSEC pin 10 */
+   "CSI0_DP0", /* GPIO_59, HSEC pin 8 */
+   "CSI0_DN1", /* GPIO_60, HSEC pin 16 */
+   "CSI0_DP1", /* GPIO_61, HSEC pin 14 */
+   "CSI0_CN", /* GPIO_62, HSEC pin 4 */
+   "CSI0_CP", /* GPIO_63, HSEC pin 2 */
+   "CSI0_DN2", /* GPIO_64, HSEC pin 22 */
+   "CSI0_DP2", /* GPIO_65, HSEC pin 20 */
+   "CSI0_DN3", /* GPIO_66, HSEC pin 28 */
+

[PATCH v2 3/5] arm64: dts: actions: Add gpio line names to Bubblegum-96 board

2018-05-19 Thread Manivannan Sadhasivam 
Add gpio line names to Actions Semi S900 based Bubblegum-96 board.

Signed-off-by: Manivannan Sadhasivam 
---
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 175 ++
 1 file changed, 175 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts 
b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index ff043c961d75..d0ba35df9015 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -34,3 +34,178 @@
status = "okay";
clocks = < CLK_UART5>;
 };
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (pin out but not routed from the chip to
+ *  anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * LSEC = Low Speed External Connector
+ * HSEC = High Speed External Connector
+ *
+ * Line names are taken from the schematic "Schematics Bubblegum96"
+ * version v1.0
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Boards naming of a line and the schematic name of
+ * the same line are in conflict, the 96Boards specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART2. Only exception is the I2C lines for which the schematic
+ * naming has been preferred. This is only for the informational
+ * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
+ * are the only ones actually used for GPIO.
+ */
+
+ {
+   gpio-line-names =
+   "GPIO-A", /* GPIO_0, LSEC pin 23 */
+   "GPIO-B", /* GPIO_1, LSEC pin 24 */
+   "GPIO-C", /* GPIO_2, LSEC pin 25 */
+   "GPIO-D", /* GPIO_3, LSEC pin 26 */
+   "GPIO-E", /* GPIO_4, LSEC pin 27 */
+   "GPIO-F", /* GPIO_5, LSEC pin 28 */
+   "GPIO-G", /* GPIO_6, LSEC pin 29 */
+   "GPIO-H", /* GPIO_7, LSEC pin 30 */
+   "GPIO-I", /* GPIO_8, LSEC pin 31 */
+   "GPIO-J", /* GPIO_9, LSEC pin 32 */
+   "NC", /* GPIO_10 */
+   "NC", /* GPIO_11 */
+   "SIRQ2_1V8", /* GPIO_12 */
+   "PCM0_OUT", /* GPIO_13 */
+   "WIFI_LED", /* GPIO_14 */
+   "PCM0_SYNC", /* GPIO_15 */
+   "PCM0_CLK", /* GPIO_16 */
+   "PCM0_IN", /* GPIO_17 */
+   "BT_LED", /* GPIO_18 */
+   "LED0", /* GPIO_19 */
+   "LED1", /* GPIO_20 */
+   "JTAG_TCK", /* GPIO_21 */
+   "JTAG_TMS", /* GPIO_22 */
+   "JTAG_TDI", /* GPIO_23 */
+   "JTAG_TDO", /* GPIO_24 */
+   "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */
+   "NC", /* GPIO_26 */
+   "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */
+   "SD0_D0", /* GPIO_28 */
+   "SD0_D1", /* GPIO_29 */
+   "SD0_D2", /* GPIO_30 */
+   "SD0_D3", /* GPIO_31 */
+   "SD1_D0", /* GPIO_32 */
+   "SD1_D1", /* GPIO_33 */
+   "SD1_D2", /* GPIO_34 */
+   "SD1_D3", /* GPIO_35 */
+   "SD0_CMD", /* GPIO_36 */
+   "SD0_CLK", /* GPIO_37 */
+   "SD1_CMD", /* GPIO_38 */
+   "SD1_CLK", /* GPIO_39 */
+   "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */
+   "SPI0_CS", /* GPIO_41, LSEC pin 12 */
+   "SPI0_DIN", /* GPIO_42, LSEC pin 10 */
+   "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */
+   "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */
+   "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */
+   "UART0_RX", /* GPIO_46, LSEC pin 7 */
+   "UART0_TX", /* GPIO_47, LSEC pin 5 */
+   "UART0_RTSB", /* GPIO_48, LSEC pin 9 */
+   "UART0_CTSB", /* GPIO_49, LSEC pin 3 */
+   "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */
+   "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */
+   "I2C0_SCLK", /* GPIO_52 */
+   "I2C0_SDATA", /* GPIO_53 */
+   "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */
+   "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */
+   "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */
+   "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */
+   "CSI0_DN0", /* GPIO_58, HSEC pin 10 */
+   "CSI0_DP0", /* GPIO_59, HSEC pin 8 */
+   "CSI0_DN1", /* GPIO_60, HSEC pin 16 */
+   "CSI0_DP1", /* GPIO_61, HSEC pin 14 */
+   "CSI0_CN", /* GPIO_62, HSEC pin 4 */
+   "CSI0_CP", /* GPIO_63, HSEC pin 2 */
+   "CSI0_DN2", /* GPIO_64, HSEC pin 22 */
+   "CSI0_DP2", /* GPIO_65, HSEC pin 20 */
+   "CSI0_DN3", /* GPIO_66, HSEC pin 28 */
+   "CSI0_DP3", /* GPIO_67,