Re: [PATCH v2 5/5] MIPS: JZ4780: DTS: Add CPU nodes

[Alexandre GRIVEAUX]

Hi Paul and other.
> Hi Alexandre,
> This should probably be something like ingenic,xburst2. JZ4780 is the
> SoC. It also should be a documented binding, but I think it would be
> worth holding off on the whole thing until we actually get SMP support
> merged - just in case we come up with a binding that doesn't actually
> work out.
>
> So I expect I'll just apply patches 1-4 for now.
>
> Thanks for working on it!

I holding the CPU patch at this time for more work later, I would like
to upstream some patchs from this repository:

https://github.com/MIPS/CI20_linux.git


How i can do that and keep the contributors history ?


Thanks for the help.

Ps: I try to unban my e-mail server from office365...

Re: [PATCH v2 5/5] MIPS: JZ4780: DTS: Add CPU nodes

[Paul Burton]

Hi Alexandre,

On Tue, Oct 01, 2019 at 09:09:48PM +0200, Alexandre GRIVEAUX wrote:
> The JZ4780 have 2 core, adding to DT.
> 
> Signed-off-by: Alexandre GRIVEAUX 
> ---
>  arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi 
> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index f928329b034b..9c7346724f1f 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -7,6 +7,23 @@
>   #size-cells = <1>;
>   compatible = "ingenic,jz4780";
>  
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "ingenic,jz4780";

This should probably be something like ingenic,xburst2. JZ4780 is the
SoC. It also should be a documented binding, but I think it would be
worth holding off on the whole thing until we actually get SMP support
merged - just in case we come up with a binding that doesn't actually
work out.

So I expect I'll just apply patches 1-4 for now.

Thanks for working on it!

Paul

> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "ingenic,jz4780";
> + device_type = "cpu";
> + reg = <1>;
> + };
> + };
> +
>   cpuintc: interrupt-controller {
>   #address-cells = <0>;
>   #interrupt-cells = <1>;
> -- 
> 2.20.1
> 

[PATCH v2 5/5] MIPS: JZ4780: DTS: Add CPU nodes

[Alexandre GRIVEAUX]

The JZ4780 have 2 core, adding to DT.

Signed-off-by: Alexandre GRIVEAUX 
---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi 
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index f928329b034b..9c7346724f1f 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -7,6 +7,23 @@
#size-cells = <1>;
compatible = "ingenic,jz4780";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "ingenic,jz4780";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "ingenic,jz4780";
+   device_type = "cpu";
+   reg = <1>;
+   };
+   };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
-- 
2.20.1