Re: [PATCH v2 6/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

2021-03-14 Thread kernel test robot
Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on stm32/stm32-next]
[also build test WARNING on robh/for-next soc/for-next v5.12-rc2 next-20210312]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/dillon-minfei-gmail-com/ARM-STM32-add-art-pi-stm32h750xbh6-board-support/20210312-142805
base:   https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git 
stm32-next
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce: make ARCH=arm dtbs_check

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 


"dtcheck warnings: (new ones prefixed by >>)"
>> arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: soc: pin-controller: {'type': 
>> 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[1]], 
>> 'ranges': [[0, 1476526080, 12288]], 'interrupt-parent': [[22]], 'st,syscfg': 
>> [[28, 8]], 'pins-are-numbered': True, 'compatible': 
>> ['st,stm32h750-pinctrl'], 'gpio@5802': {'gpio-controller': True, 
>> '#gpio-cells': [[2]], 'reg': [[0, 1024]], 'clocks': [[2, 86]], 
>> 'st,bank-name': ['GPIOA'], 'interrupt-controller': True, '#interrupt-cells': 
>> [[2]], 'phandle': [[10]]}, 'gpio@58020400': {'gpio-controller': True, 
>> '#gpio-cells': [[2]], 'reg': [[1024, 1024]], 'clocks': [[2, 85]], 
>> 'st,bank-name': ['GPIOB'], 'interrupt-controller': True, '#interrupt-cells': 
>> [[2]]}, 'gpio@58020800': {'gpio-controller': True, '#gpio-cells': [[2]], 
>> 'reg': [[2048, 1024]], 'clocks': [[2, 84]], 'st,bank-name': ['GPIOC'], 
>> 'interrupt-controller': True, '#interrupt-cells': [[2]], 'phandle': [[6]]}, 
>> 'gpio@58020c00': {'gpio-controller': True, '#gpio-cells': [[2]], 'reg': 
 [[3072, 1024]], 'clocks': [[2, 83]], 'st,bank-name': ['GPIOD'], 
'interrupt-controller': True, '#interrupt-cells': [[2]], 'phandle': [[4]]}, 
'gpio@58021000': {'gpio-controller': True, '#gpio-cells': [[2]], 'reg': [[4096, 
1024]], 'clocks': [[2, 82]], 'st,bank-name': ['GPIOE'], 'interrupt-controller': 
True, '#interrupt-cells': [[2]]}, 'gpio@58021400': {'gpio-controller': True, 
'#gpio-cells': [[2]], 'reg': [[5120, 1024]], 'clocks': [[2, 81]], 
'st,bank-name': ['GPIOF'], 'interrupt-controller': True, '#interrupt-cells': 
[[2]]}, 'gpio@58021800': {'gpio-controller': True, '#gpio-cells': [[2]], 'reg': 
[[6144, 1024]], 'clocks': [[2, 80]], 'st,bank-name': ['GPIOG'], 
'interrupt-controller': True, '#interrupt-cells': [[2]]}, 'gpio@58021c00': 
{'gpio-controller': True, '#gpio-cells': [[2]], 'reg': [[7168, 1024]], 
'clocks': [[2, 79]], 'st,bank-name': ['GPIOH'], 'interrupt-controller': True, 
'#interrupt-cells': [[2]]}, 'gpio@58022000': {'gpio-controller': True, 
'#gpio-cells': [[2]], 'reg': [[8192, 1
 024]], 'clocks': [[2, 78]], 'st,bank-name': ['GPIOI'], 'interrupt-controller': 
True, '#interrupt-cells': [[2]], 'phandle': [[7]]}, 'gpio@58022400': 
{'gpio-controller': True, '#gpio-cells': [[2]], 'reg': [[9216, 1024]], 
'clocks': [[2, 77]], 'st,bank-name': ['GPIOJ'], 'interrupt-controller': True, 
'#interrupt-cells': [[2]]}, 'gpio@58022800': {'gpio-controller': True, 
'#gpio-cells': [[2]], 'reg': [[10240, 1024]], 'clocks': [[2, 76]], 
'st,bank-name': ['GPIOK'], 'interrupt-controller': True, '#interrupt-cells': 
[[2]]}, 'i2c1-0': {'pins': {'pinmux': [[5637], [5893]], 'bias-disable': True, 
'drive-open-drain': True, 'slew-rate': [[0]]}}, 'rmii-0': {'phandle': [[29]], 
'pins': {'pinmux': [[27404], [27916], [27660], [9228], [9484], [1804], [8460], 
[524], [268]], 'slew-rate': [[2]]}}, 'sdmmc1-b4-0': {'phandle': [[14]], 'pins': 
{'pinmux': [[10253], [10509], [10765], [11021], [11277], [12813]], 'slew-rate': 
[[3]], 'drive-push-pull': True, 'bias-disable': True}}, 'sdmmc1-b4-od-0': 
{'phandle': [[15
 ]], 'pins1': {'pinmux': [[10253], [10509], [10765], [11021], [11277]], 
'slew-rate': [[3]], 'drive-push-pull': True, 'bias-disable': True}, 'pins2': 
{'pinmux': [[12813]], 'slew-rate': [[3]], 'drive-open-drain': True, 
'bias-disable': True}}, 'sdmmc1-b4-sleep-0': {'phandle': [[16]], 'pins': 
{'pinmux': [[10257], [10513], [10769], [11025], [11281], [12817]]}}, 
'sdmmc2-b4-0': {'phandle': [[18]], 'pins': {'pinmux': [[7690], [7946], [4874], 
[5130], [13836], [14092]], 'slew-rate': [[3]], 'drive-push-pull': True, 
'bias-disable': True}}, 'sdmmc2-b4-od-0': {'phandle': [[19]], 'pins1': 
{'pinmux': [[7690], [7946], [4874], [5130], [13836]], 'slew-rate': [[3]], 
'drive-push-pull': True, 'bias-disable': True}, 'pins2': {'pinmux': [[14092]], 
'slew-rate': [[3]], 'drive-open-drain': True, 'bias-disable': True}}, 
'sdmmc2-b4-sleep-0': {'phandle': [[20]], 'pins': {'pinmux': [[7697], [7953], 
[4881], [5137], [13841], [14097]]}}, 'sdmmc1-dir-0': {'pins1': {'pinmux': 
[[9737], [9993], [6408]], 'slew-rate': [[3]
 ], 'drive-push-pull': True, 'bias-pull-up': True}, 'pins2': {'pinmux': 
[[6152]], 

[PATCH v2 6/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

2021-03-11 Thread dillon . minfei
From: dillon min 

This patchset has following changes:

- introduce stm32h750.dtsi to support stm32h750 value line
- add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile)
- add dts binding usart3 for bt, uart4 for console
  usart3/uart4 pinctrl in stm32h7-pinctrl.dtsi
  usart3/uart4 register in stm32h743.dtsi
- add dts binding sdmmc2 for wifi
  sdmmc2 pinctrl in stm32h7-pinctrl.dtsi
  sdmmc2 register in stm32h743.dtsi
- add spi1 pinctrl in stm32h7-pinctrl.dtsi for spi flash
- add stm32h750-art-pi.dts to support art-pi board

art-pi board component:
- 8MiB qspi flash
- 16MiB spi flash
- 32MiB sdram
- ap6212 wifi

the detail board information can be found at:
https://art-pi.gitee.io/website/

Signed-off-by: dillon min 
---
v2:
- fix author name/copyright mistake
- make item in stm32h750i-art-pi.dts sort by letter

 arch/arm/boot/dts/Makefile  |   1 +
 arch/arm/boot/dts/stm32h7-pinctrl.dtsi  |  87 
 arch/arm/boot/dts/stm32h743.dtsi|  30 +
 arch/arm/boot/dts/stm32h750.dtsi|   5 +
 arch/arm/boot/dts/stm32h750i-art-pi.dts | 228 
 5 files changed, 351 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
 create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e75e..a19c5ab9df84 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32746g-eval.dtb \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
+   stm32h750i-art-pi.dtb \
stm32mp153c-dhcom-drc02.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-dhcor-avenger96.dtb \
diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
index 9fcc1e3ba925..0d08225a16de 100644
--- a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
@@ -231,6 +231,50 @@
};
};
 
+   sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+   pins {
+   pinmux = , 
/* SDMMC1_D0 */
+, 
/* SDMMC1_D1 */
+, 
/* SDMMC1_D2 */
+, 
/* SDMMC1_D3 */
+, 
/* SDMMC1_CK */
+; 
/* SDMMC1_CMD */
+   slew-rate = <3>;
+   drive-push-pull;
+   bias-disable;
+   };
+   };
+
+   sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+   pins1 {
+   pinmux = , 
/* SDMMC2_D0 */
+, 
/* SDMMC1_D1 */
+, 
/* SDMMC1_D2 */
+, 
/* SDMMC1_D3 */
+; 
/* SDMMC1_CK */
+   slew-rate = <3>;
+   drive-push-pull;
+   bias-disable;
+   };
+   pins2{
+   pinmux = ; 
/* SDMMC1_CMD */
+   slew-rate = <3>;
+   drive-open-drain;
+   bias-disable;
+   };
+   };
+
+   sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+   pins {
+   pinmux = , /* SDMMC1_D0 */
+, /* SDMMC1_D1 */
+, /* SDMMC1_D2 */
+, /* SDMMC1_D3 */
+, /* SDMMC1_CK */
+; /* SDMMC1_CMD */
+   };
+   };
+
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = , 
/* SDMMC1_D0DIR */
@@ -281,6 +325,32 @@
};
};
 
+   usart3_pins: usart3-0 {
+   pins1 {
+   pinmux = ; 
/* USART3_TX */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+