[PATCH v2 7/7] platform/x86: mlx-platform: Add mlxreg-io platform driver activation

2018-05-06 Thread Vadim Pasternak 
Add mlxreg-io platform driver activation. Access driver uses the same
regmap infrastructure as others Mellanox platform drivers.
Specific registers description for default platform data configuration are
added to mlx-platform. There are the registers for resets control, reset
causes monitoring, programmable devices version reading and mux select
control. This platform data is passed to mlxreg-io driver. Also some
default values for the register are set at initialization time through
the regmap infrastructure, which are necessary for moving write protection
from the general purpose registers, which are used by mlxreg-io for
write access.

Signed-off-by: Vadim Pasternak 
---
 drivers/platform/x86/mlx-platform.c | 159 +++-
 1 file changed, 157 insertions(+), 2 deletions(-)

diff --git a/drivers/platform/x86/mlx-platform.c 
b/drivers/platform/x86/mlx-platform.c
index a0fd9aa..87ddd3a 100644
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -47,11 +47,18 @@
 /* LPC bus IO offsets */
 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
+#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET  0x00
+#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET  0x01
+#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET0x1d
 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET   0x20
 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET   0x21
 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET   0x22
 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET   0x23
 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET   0x24
+#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET0x30
+#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET0x31
+#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET0x32
+#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET0x33
 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET   0x3a
 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET  0x3b
 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
@@ -122,12 +129,14 @@
  * @pdev_mux - array of mux platform devices
  * @pdev_hotplug - hotplug platform devices
  * @pdev_led - led platform devices
+ * @pdev_io_regs - register access platform devices
  */
 struct mlxplat_priv {
struct platform_device *pdev_i2c;
struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
struct platform_device *pdev_hotplug;
struct platform_device *pdev_led;
+   struct platform_device *pdev_io_regs;
 };
 
 /* Regions for LPC I2C controller and LPC base register space */
@@ -813,6 +822,98 @@ static struct mlxreg_core_platform_data 
mlxplat_default_ng_led_data = {
.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
 };
 
+/* Platform register access default */
+static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
+   {
+   .label = "cpld1_version",
+   .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
+   .bit = GENMASK(7, 0),
+   .mode = 0444,
+   },
+   {
+   .label = "cpld2_version",
+   .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
+   .bit = GENMASK(7, 0),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_long_pb",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(0),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_short_pb",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(1),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_aux_pwr_or_ref",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(2),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_main_pwr_fail",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(3),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_sw_reset",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(4),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_fw_reset",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(5),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_hotswap_or_wd",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(6),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_asic_thermal",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(7),
+   .mode = 0444,
+   },
+   {
+   .label = "psu1_on",
+   .reg =

[PATCH v2 7/7] platform/x86: mlx-platform: Add mlxreg-io platform driver activation

2018-05-06 Thread Vadim Pasternak 
Add mlxreg-io platform driver activation. Access driver uses the same
regmap infrastructure as others Mellanox platform drivers.
Specific registers description for default platform data configuration are
added to mlx-platform. There are the registers for resets control, reset
causes monitoring, programmable devices version reading and mux select
control. This platform data is passed to mlxreg-io driver. Also some
default values for the register are set at initialization time through
the regmap infrastructure, which are necessary for moving write protection
from the general purpose registers, which are used by mlxreg-io for
write access.

Signed-off-by: Vadim Pasternak 
---
 drivers/platform/x86/mlx-platform.c | 159 +++-
 1 file changed, 157 insertions(+), 2 deletions(-)

diff --git a/drivers/platform/x86/mlx-platform.c 
b/drivers/platform/x86/mlx-platform.c
index a0fd9aa..87ddd3a 100644
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -47,11 +47,18 @@
 /* LPC bus IO offsets */
 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
+#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET  0x00
+#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET  0x01
+#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET0x1d
 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET   0x20
 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET   0x21
 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET   0x22
 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET   0x23
 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET   0x24
+#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET0x30
+#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET0x31
+#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET0x32
+#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET0x33
 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET   0x3a
 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET  0x3b
 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
@@ -122,12 +129,14 @@
  * @pdev_mux - array of mux platform devices
  * @pdev_hotplug - hotplug platform devices
  * @pdev_led - led platform devices
+ * @pdev_io_regs - register access platform devices
  */
 struct mlxplat_priv {
struct platform_device *pdev_i2c;
struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
struct platform_device *pdev_hotplug;
struct platform_device *pdev_led;
+   struct platform_device *pdev_io_regs;
 };
 
 /* Regions for LPC I2C controller and LPC base register space */
@@ -813,6 +822,98 @@ static struct mlxreg_core_platform_data 
mlxplat_default_ng_led_data = {
.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
 };
 
+/* Platform register access default */
+static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
+   {
+   .label = "cpld1_version",
+   .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
+   .bit = GENMASK(7, 0),
+   .mode = 0444,
+   },
+   {
+   .label = "cpld2_version",
+   .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
+   .bit = GENMASK(7, 0),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_long_pb",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(0),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_short_pb",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(1),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_aux_pwr_or_ref",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(2),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_main_pwr_fail",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(3),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_sw_reset",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(4),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_fw_reset",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(5),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_hotswap_or_wd",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(6),
+   .mode = 0444,
+   },
+   {
+   .label = "cause_asic_thermal",
+   .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+   .mask = GENMASK(7, 0) & ~BIT(7),
+   .mode = 0444,
+   },
+   {
+   .label = "psu1_on",
+   .reg =