Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 272 +---
drivers/gpu/drm/vc4/vc4_drv.h | 5 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 298 ++-
3 files changed, 309 insertions(+), 266 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 983ae476c203..93161b98e22a 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -206,48 +206,6 @@ static void vc4_crtc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
}
-static void
-vc4_crtc_lut_load(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
- u32 i;
-
- /* The LUT memory is laid out with each HVS channel in order,
-* each of which takes 256 writes for R, 256 for G, then 256
-* for B.
-*/
- HVS_WRITE(SCALER_GAMADDR,
- SCALER_GAMADDR_AUTOINC |
- (vc4_crtc_state->assigned_channel * 3 * crtc->gamma_size));
-
- for (i = 0; i < crtc->gamma_size; i++)
- HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
- for (i = 0; i < crtc->gamma_size; i++)
- HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
- for (i = 0; i < crtc->gamma_size; i++)
- HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
-}
-
-static void
-vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
-{
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- struct drm_color_lut *lut = crtc->state->gamma_lut->data;
- u32 length = drm_color_lut_size(crtc->state->gamma_lut);
- u32 i;
-
- for (i = 0; i < length; i++) {
- vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
- vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
- vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
- }
-
- vc4_crtc_lut_load(crtc);
-}
-
static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
{
u32 fifo_len_bytes = vc4_crtc->data->fifo_depth;
@@ -403,12 +361,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- struct drm_display_mode *mode = &crtc->state->adjusted_mode;
- bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
bool debug_dump_regs = false;
if (debug_dump_regs) {
@@ -418,42 +372,10 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
drm_print_regset32(&p, &vc4_crtc->regset);
}
- if (vc4_crtc->data->hvs_output == 2) {
- u32 dispctrl;
- u32 dsp3_mux;
-
- /*
-* SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
-* FIFO X'.
-* SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
-*
-* DSP3 is connected to FIFO2 unless the transposer is
-* enabled. In this case, FIFO 2 is directly accessed by the
-* TXP IP, and we need to disable the FIFO2 -> pixelvalve1
-* route.
-*/
- if (vc4_state->feed_txp)
- dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
- else
- dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
-
- dispctrl = HVS_READ(SCALER_DISPCTRL) &
- ~SCALER_DISPCTRL_DSP3_MUX_MASK;
- HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
- }
-
if (!vc4_state->feed_txp)
vc4_crtc_config_pv(crtc);
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
- SCALER_DISPBKGND_AUTOHS |
- ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
- (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
-
- /* Reload the LUT, since the SRAMs would have been disabled if
-* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
-*/
- vc4_crtc_lut_load(crtc);
+ vc4_hvs_mode_set_nofb(crtc);
if (debug_dump_regs) {
struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
@@ -475,11 +397,9 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct drm_device *dev = crtc->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(old_
