Re: [PATCH v3 07/10] pinctrl: Ingenic: Add pinctrl driver for JZ4750.

2021-03-25 Thread Zhou Yanjie 



On 2021/3/23 上午2:20, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v3:
    New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 137 
++

 1 file changed, 137 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index 25458d6..d98767b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -85,6 +85,7 @@ enum jz_version {
 ID_JZ4730,
 ID_JZ4740,
 ID_JZ4725B,
+    ID_JZ4750,
 ID_JZ4760,
 ID_JZ4770,
 ID_JZ4780,
@@ -424,6 +425,138 @@ static const struct ingenic_chip_info 
jz4725b_chip_info = {

 .pull_downs = jz4740_pull_downs,
 };

+static const u32 jz4750_pull_ups[6] = {
+    0x, 0x, 0x3fff, 0x7fff, 0x1fff3fff, 
0x00ff,

+};
+
+static const u32 jz4750_pull_downs[6] = {
+    0x, 0x, 0x, 0x, 0x, 
0x,

+};
+
+static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
+static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
+static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
+static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
+static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
+static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
+static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
+static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
+static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
+static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
+static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
+static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
+static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4750_cim_pins[] = {
+    0x89, 0x8b, 0x8a, 0x88,
+    0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4750_lcd_8bit_pins[] = {
+    0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x72, 0x73, 0x74,
+};
+static int jz4750_lcd_16bit_pins[] = {
+    0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x75,
+};
+static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4750_lcd_18bit_tft_pins[] = { 0x78, 0x79, 0x76, 0x77, };
+static int jz4750_nand_cs1_pins[] = { 0x55, };
+static int jz4750_nand_cs2_pins[] = { 0x56, };
+static int jz4750_nand_cs3_pins[] = { 0x57, };
+static int jz4750_nand_cs4_pins[] = { 0x58, };
+static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4750_pwm_pwm0_pins[] = { 0x94, };
+static int jz4750_pwm_pwm1_pins[] = { 0x95, };
+static int jz4750_pwm_pwm2_pins[] = { 0x96, };
+static int jz4750_pwm_pwm3_pins[] = { 0x97, };
+static int jz4750_pwm_pwm4_pins[] = { 0x98, };
+static int jz4750_pwm_pwm5_pins[] = { 0x99, };
+
+static const struct group_desc jz4750_groups[] = {
+    INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
+    INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
+    INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
+    INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
+    INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
+    INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
+    INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
+    INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
+    INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
+    INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
+    INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
+    INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
+    INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
+    INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
+    INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
+    INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
+    INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
+    INGENIC_PIN_GROUP("lcd-18bit-tft", jz4750_lcd_18bit_tft, 0),
+    { "lcd-no-pins", },


Please drop "lcd-no-pins" from your patches, it is pointless.



Sure.



Cheers,
-Paul


+    INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
+    INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
+    INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
+    INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
+    INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
+    INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
+    INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
+    INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
+    INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
+    INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
+    INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
+};
+
+static const char *jz4750_uart0_groups[] = { "uart0-data", 
"uart0-hwflow", };
+static const char *jz4750_uart1_groups[] = { "uart1-data", 
"uart1-hwflow", };

+static const char *jz4750_uart2_groups[] = { "uart2-data", };
+static const char *jz4750_uart3_groups[] = { "uart3-data",

Re: [PATCH v3 07/10] pinctrl: Ingenic: Add pinctrl driver for JZ4750.

2021-03-22 Thread Paul Cercueil 




Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v3:
New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 137 
++

 1 file changed, 137 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index 25458d6..d98767b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -85,6 +85,7 @@ enum jz_version {
ID_JZ4730,
ID_JZ4740,
ID_JZ4725B,
+   ID_JZ4750,
ID_JZ4760,
ID_JZ4770,
ID_JZ4780,
@@ -424,6 +425,138 @@ static const struct ingenic_chip_info 
jz4725b_chip_info = {

.pull_downs = jz4740_pull_downs,
 };

+static const u32 jz4750_pull_ups[6] = {
+	0x, 0x, 0x3fff, 0x7fff, 0x1fff3fff, 
0x00ff,

+};
+
+static const u32 jz4750_pull_downs[6] = {
+	0x, 0x, 0x, 0x, 0x, 
0x,

+};
+
+static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
+static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
+static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
+static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
+static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
+static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
+static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
+static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
+static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
+static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
+static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
+static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
+static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4750_cim_pins[] = {
+   0x89, 0x8b, 0x8a, 0x88,
+   0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4750_lcd_8bit_pins[] = {
+   0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x72, 0x73, 0x74,
+};
+static int jz4750_lcd_16bit_pins[] = {
+   0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x75,
+};
+static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4750_lcd_18bit_tft_pins[] = { 0x78, 0x79, 0x76, 0x77, };
+static int jz4750_nand_cs1_pins[] = { 0x55, };
+static int jz4750_nand_cs2_pins[] = { 0x56, };
+static int jz4750_nand_cs3_pins[] = { 0x57, };
+static int jz4750_nand_cs4_pins[] = { 0x58, };
+static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4750_pwm_pwm0_pins[] = { 0x94, };
+static int jz4750_pwm_pwm1_pins[] = { 0x95, };
+static int jz4750_pwm_pwm2_pins[] = { 0x96, };
+static int jz4750_pwm_pwm3_pins[] = { 0x97, };
+static int jz4750_pwm_pwm4_pins[] = { 0x98, };
+static int jz4750_pwm_pwm5_pins[] = { 0x99, };
+
+static const struct group_desc jz4750_groups[] = {
+   INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
+   INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
+   INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
+   INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
+   INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
+   INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
+   INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
+   INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
+   INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
+   INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
+   INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
+   INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
+   INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
+   INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
+   INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
+   INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
+   INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
+   INGENIC_PIN_GROUP("lcd-18bit-tft", jz4750_lcd_18bit_tft, 0),
+   { "lcd-no-pins", },


Please drop "lcd-no-pins" from your patches, it is pointless.

Cheers,
-Paul


+   INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
+   INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
+   INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
+   INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
+   INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
+   INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
+   INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
+   INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
+   INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
+   INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
+   INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
+};
+
+static const char *jz4750_uart0_groups[] = { "uart0-data", 
"uart0-hwflow", };
+static const char *jz4750_uart1_groups[] = { "uart1-data", 
"uart1-hwflow", };

+static const char *jz4750_uart2_groups[] = { "uart2-data", };

[PATCH v3 07/10] pinctrl: Ingenic: Add pinctrl driver for JZ4750.

2021-03-17 Thread Zhou Yanjie 
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v3:
New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 137 ++
 1 file changed, 137 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 25458d6..d98767b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -85,6 +85,7 @@ enum jz_version {
ID_JZ4730,
ID_JZ4740,
ID_JZ4725B,
+   ID_JZ4750,
ID_JZ4760,
ID_JZ4770,
ID_JZ4780,
@@ -424,6 +425,138 @@ static const struct ingenic_chip_info jz4725b_chip_info = 
{
.pull_downs = jz4740_pull_downs,
 };
 
+static const u32 jz4750_pull_ups[6] = {
+   0x, 0x, 0x3fff, 0x7fff, 0x1fff3fff, 0x00ff,
+};
+
+static const u32 jz4750_pull_downs[6] = {
+   0x, 0x, 0x, 0x, 0x, 0x,
+};
+
+static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
+static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
+static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
+static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
+static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
+static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
+static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
+static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
+static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
+static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
+static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
+static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
+static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4750_cim_pins[] = {
+   0x89, 0x8b, 0x8a, 0x88,
+   0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4750_lcd_8bit_pins[] = {
+   0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x72, 0x73, 0x74,
+};
+static int jz4750_lcd_16bit_pins[] = {
+   0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x75,
+};
+static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4750_lcd_18bit_tft_pins[] = { 0x78, 0x79, 0x76, 0x77, };
+static int jz4750_nand_cs1_pins[] = { 0x55, };
+static int jz4750_nand_cs2_pins[] = { 0x56, };
+static int jz4750_nand_cs3_pins[] = { 0x57, };
+static int jz4750_nand_cs4_pins[] = { 0x58, };
+static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4750_pwm_pwm0_pins[] = { 0x94, };
+static int jz4750_pwm_pwm1_pins[] = { 0x95, };
+static int jz4750_pwm_pwm2_pins[] = { 0x96, };
+static int jz4750_pwm_pwm3_pins[] = { 0x97, };
+static int jz4750_pwm_pwm4_pins[] = { 0x98, };
+static int jz4750_pwm_pwm5_pins[] = { 0x99, };
+
+static const struct group_desc jz4750_groups[] = {
+   INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
+   INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
+   INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
+   INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
+   INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
+   INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
+   INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
+   INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
+   INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
+   INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
+   INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
+   INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
+   INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
+   INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
+   INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
+   INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
+   INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
+   INGENIC_PIN_GROUP("lcd-18bit-tft", jz4750_lcd_18bit_tft, 0),
+   { "lcd-no-pins", },
+   INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
+   INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
+   INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
+   INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
+   INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
+   INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
+   INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
+   INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
+   INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
+   INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
+   INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
+};
+
+static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
+static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
+static const char *jz4750_uart2_groups[] = { "uart2-data", };
+static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
+static const char *jz4750_mmc0_groups[] = {
+   "mmc0-1bit",