Re: [PATCH v3 1/3] clk: sifive: Extract prci core to common base

2020-11-15 Thread Zong Li 
On Thu, Nov 12, 2020 at 2:02 PM Stephen Boyd  wrote:
>
> Quoting Pragnesh Patel (2020-11-11 01:51:17)
> > >+#define RCI_GEMGXLPLLCFG1_CKE_SHIFT   24
> > >+#define PRCI_GEMGXLPLLCFG1_CKE_MASK   (0x1 <<
> > >PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
> >
> > Same here, Other than this
> >
> > Reviewed-by: Pragnesh Patel 
> >
>
> Please trim your replies

In v4 patch version, I change the definition of macros to 31 from 24 as follows:
- PRCI_CLTXPLLCFG1_CKE_SHIFT
- PRCI_DVFSCOREPLLCFG1_CKE_SHIFT
- PRCI_HFPCLKPLLCFG1_CKE_SHIFT
- PRCI_DDRPLLCFG1_CKE_SHIFT
- RCI_GEMGXLPLLCFG1_CKE_SHIFT

Re: [PATCH v3 1/3] clk: sifive: Extract prci core to common base

2020-11-11 Thread Zong Li 
On Wed, Nov 11, 2020 at 5:51 PM Pragnesh Patel
 wrote:
>
> Hi Zong,
>
> >-Original Message-
> >From: Zong Li 
> >Sent: 11 November 2020 15:05
> >To: Paul Walmsley ( Sifive) ; pal...@dabbelt.com;
> >sb...@kernel.org; sch...@linux-m68k.org; Pragnesh Patel
> >; a...@eecs.berkeley.edu;
> >mturque...@baylibre.com; Yash Shah ; linux-
> >ker...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> >ri...@lists.infradead.org
> >Cc: Zong Li 
> >Subject: [PATCH v3 1/3] clk: sifive: Extract prci core to common base
> >
> >Extract common core of prci driver to an independent file, it could allow 
> >other
> >chips to reuse it. Separate SoCs-dependent code 'fu540'
> >from prci core, then we can easily add 'fu740' later.
> >
> >Almost these changes are code movement. The different is adding the private
> >data for each SoC use, so it needs to get match data in probe callback 
> >function,
> >then use the data for initialization.
> >
> >Signed-off-by: Zong Li 
> >---
> > drivers/clk/sifive/Makefile   |   2 +
> > drivers/clk/sifive/fu540-prci.c   | 586 +-
> > drivers/clk/sifive/fu540-prci.h   |  21 +
> > .../sifive/{fu540-prci.c => sifive-prci.c}| 381 +++-
> > drivers/clk/sifive/sifive-prci.h  | 201 ++
> > 5 files changed, 323 insertions(+), 868 deletions(-)  create mode 100644
> >drivers/clk/sifive/fu540-prci.h  copy drivers/clk/sifive/{fu540-prci.c => 
> >sifive-
> >prci.c} (45%)  create mode 100644 drivers/clk/sifive/sifive-prci.h
> >
> >diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index
> >0797f14fef6b..627effe2ece1 100644
> >--- a/drivers/clk/sifive/Makefile
> >+++ b/drivers/clk/sifive/Makefile
> >@@ -1,2 +1,4 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> >+obj-y += sifive-prci.o
> >+
> > obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)   += fu540-prci.o
> >diff --git a/drivers/clk/sifive/fu540-prci.c 
> >b/drivers/clk/sifive/fu540-prci.c index
> >a8901f90a61a..840b97bfff85 100644
> >--- a/drivers/clk/sifive/fu540-prci.c
> >+++ b/drivers/clk/sifive/fu540-prci.c
> >@@ -3,6 +3,7 @@
> >  * Copyright (C) 2018-2019 SiFive, Inc.
> >  * Wesley Terpstra
> >  * Paul Walmsley
> >+ * Zong Li
> >  *
> >  * This program is free software; you can redistribute it and/or modify
> >  * it under the terms of the GNU General Public License version 2 as @@ -
> >13,475 +14,48 @@
> >  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >  * GNU General Public License for more details.
> >  *
> >- * The FU540 PRCI implements clock and reset control for the SiFive
> >- * FU540-C000 chip.  This driver assumes that it has sole control
> >- * over all PRCI resources.
> >- *
> >- * This driver is based on the PRCI driver written by Wesley Terpstra:
> >- * https://github.com/riscv/riscv-
> >linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
> >- *
> >  * References:
> >  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
> >  */
> >
> > #include 
> >-#include 
> >-#include 
> >-#include 
> >-#include 
> >-#include 
> >-#include 
> > #include 
> >-#include 
> >-#include 
> >-#include 
> >-#include 
> >-
> >-/*
> >- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
> >- * hfclk and rtcclk
> >- */
> >-#define EXPECTED_CLK_PARENT_COUNT 2
> >-
> >-/*
> >- * Register offsets and bitmasks
> >- */
> >-
> >-/* COREPLLCFG0 */
> >-#define PRCI_COREPLLCFG0_OFFSET   0x4
> >-# define PRCI_COREPLLCFG0_DIVR_SHIFT  0
> >-# define PRCI_COREPLLCFG0_DIVR_MASK   (0x3f <<
> >PRCI_COREPLLCFG0_DIVR_SHIFT)
> >-# define PRCI_COREPLLCFG0_DIVF_SHIFT  6
> >-# define PRCI_COREPLLCFG0_DIVF_MASK   (0x1ff <<
> >PRCI_COREPLLCFG0_DIVF_SHIFT)
> >-# define PRCI_COREPLLCFG0_DIVQ_SHIFT  15
> >-# define PRCI_COREPLLCFG0_DIVQ_MASK   (0x7 <<
> >PRCI_COREPLLCFG0_DIVQ_SHIFT)
> >-# define PRCI_COREPLLCFG0_RANGE_SHIFT 18
> >-# define PRCI_COREPLLCFG0_RANGE_MASK  (0x7 <<
> >PRCI_COREPLLCFG0_RANGE_SHIFT)
> >-# define PRCI_COREPLLCFG0_BYPASS_SHIFT24
> >-# define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 <<
> >PRCI_COREPLLCFG0_BYPASS_SHIFT)
> >-# define PRCI_COREPLLCFG0_FS

RE: [PATCH v3 1/3] clk: sifive: Extract prci core to common base

2020-11-11 Thread Pragnesh Patel 
Hi Zong,

>-Original Message-
>From: Zong Li 
>Sent: 11 November 2020 15:05
>To: Paul Walmsley ( Sifive) ; pal...@dabbelt.com;
>sb...@kernel.org; sch...@linux-m68k.org; Pragnesh Patel
>; a...@eecs.berkeley.edu;
>mturque...@baylibre.com; Yash Shah ; linux-
>ker...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ri...@lists.infradead.org
>Cc: Zong Li 
>Subject: [PATCH v3 1/3] clk: sifive: Extract prci core to common base
>
>Extract common core of prci driver to an independent file, it could allow other
>chips to reuse it. Separate SoCs-dependent code 'fu540'
>from prci core, then we can easily add 'fu740' later.
>
>Almost these changes are code movement. The different is adding the private
>data for each SoC use, so it needs to get match data in probe callback 
>function,
>then use the data for initialization.
>
>Signed-off-by: Zong Li 
>---
> drivers/clk/sifive/Makefile   |   2 +
> drivers/clk/sifive/fu540-prci.c   | 586 +-
> drivers/clk/sifive/fu540-prci.h   |  21 +
> .../sifive/{fu540-prci.c => sifive-prci.c}| 381 +++-
> drivers/clk/sifive/sifive-prci.h  | 201 ++
> 5 files changed, 323 insertions(+), 868 deletions(-)  create mode 100644
>drivers/clk/sifive/fu540-prci.h  copy drivers/clk/sifive/{fu540-prci.c => 
>sifive-
>prci.c} (45%)  create mode 100644 drivers/clk/sifive/sifive-prci.h
>
>diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index
>0797f14fef6b..627effe2ece1 100644
>--- a/drivers/clk/sifive/Makefile
>+++ b/drivers/clk/sifive/Makefile
>@@ -1,2 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
>+obj-y += sifive-prci.o
>+
> obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)   += fu540-prci.o
>diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c 
>index
>a8901f90a61a..840b97bfff85 100644
>--- a/drivers/clk/sifive/fu540-prci.c
>+++ b/drivers/clk/sifive/fu540-prci.c
>@@ -3,6 +3,7 @@
>  * Copyright (C) 2018-2019 SiFive, Inc.
>  * Wesley Terpstra
>  * Paul Walmsley
>+ * Zong Li
>  *
>  * This program is free software; you can redistribute it and/or modify
>  * it under the terms of the GNU General Public License version 2 as @@ -
>13,475 +14,48 @@
>  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  * GNU General Public License for more details.
>  *
>- * The FU540 PRCI implements clock and reset control for the SiFive
>- * FU540-C000 chip.  This driver assumes that it has sole control
>- * over all PRCI resources.
>- *
>- * This driver is based on the PRCI driver written by Wesley Terpstra:
>- * https://github.com/riscv/riscv-
>linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
>- *
>  * References:
>  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
>  */
>
> #include 
>-#include 
>-#include 
>-#include 
>-#include 
>-#include 
>-#include 
> #include 
>-#include 
>-#include 
>-#include 
>-#include 
>-
>-/*
>- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
>- * hfclk and rtcclk
>- */
>-#define EXPECTED_CLK_PARENT_COUNT 2
>-
>-/*
>- * Register offsets and bitmasks
>- */
>-
>-/* COREPLLCFG0 */
>-#define PRCI_COREPLLCFG0_OFFSET   0x4
>-# define PRCI_COREPLLCFG0_DIVR_SHIFT  0
>-# define PRCI_COREPLLCFG0_DIVR_MASK   (0x3f <<
>PRCI_COREPLLCFG0_DIVR_SHIFT)
>-# define PRCI_COREPLLCFG0_DIVF_SHIFT  6
>-# define PRCI_COREPLLCFG0_DIVF_MASK   (0x1ff <<
>PRCI_COREPLLCFG0_DIVF_SHIFT)
>-# define PRCI_COREPLLCFG0_DIVQ_SHIFT  15
>-# define PRCI_COREPLLCFG0_DIVQ_MASK   (0x7 <<
>PRCI_COREPLLCFG0_DIVQ_SHIFT)
>-# define PRCI_COREPLLCFG0_RANGE_SHIFT 18
>-# define PRCI_COREPLLCFG0_RANGE_MASK  (0x7 <<
>PRCI_COREPLLCFG0_RANGE_SHIFT)
>-# define PRCI_COREPLLCFG0_BYPASS_SHIFT24
>-# define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 <<
>PRCI_COREPLLCFG0_BYPASS_SHIFT)
>-# define PRCI_COREPLLCFG0_FSE_SHIFT   25
>-# define PRCI_COREPLLCFG0_FSE_MASK(0x1 <<
>PRCI_COREPLLCFG0_FSE_SHIFT)
>-# define PRCI_COREPLLCFG0_LOCK_SHIFT  31
>-# define PRCI_COREPLLCFG0_LOCK_MASK   (0x1 <<
>PRCI_COREPLLCFG0_LOCK_SHIFT)
>-
>-/* DDRPLLCFG0 */
>-#define PRCI_DDRPLLCFG0_OFFSET0xc
>-# define PRCI_DDRPLLCFG0_DIVR_SHIFT   0
>-# define PRCI_DDRPLLCFG0_DIVR_MASK(0x3f <<
>PRCI_DDRPLLCFG0_DIVR_SHIFT)
>-# define PRCI_DDRPLLCFG0_DIVF_SHIFT   6
>-# define PRCI_DDRPLLCFG0_DIVF_MASK(0x1ff <<
>PRCI_DDRPLLCFG0_DIVF_SHIFT)

[PATCH v3 1/3] clk: sifive: Extract prci core to common base

2020-11-11 Thread Zong Li 
Extract common core of prci driver to an independent file, it could
allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
from prci core, then we can easily add 'fu740' later.

Almost these changes are code movement. The different is adding the
private data for each SoC use, so it needs to get match data in probe
callback function, then use the data for initialization.

Signed-off-by: Zong Li 
---
 drivers/clk/sifive/Makefile   |   2 +
 drivers/clk/sifive/fu540-prci.c   | 586 +-
 drivers/clk/sifive/fu540-prci.h   |  21 +
 .../sifive/{fu540-prci.c => sifive-prci.c}| 381 +++-
 drivers/clk/sifive/sifive-prci.h  | 201 ++
 5 files changed, 323 insertions(+), 868 deletions(-)
 create mode 100644 drivers/clk/sifive/fu540-prci.h
 copy drivers/clk/sifive/{fu540-prci.c => sifive-prci.c} (45%)
 create mode 100644 drivers/clk/sifive/sifive-prci.h

diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index 0797f14fef6b..627effe2ece1 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,2 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
+obj-y += sifive-prci.o
+
 obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index a8901f90a61a..840b97bfff85 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2018-2019 SiFive, Inc.
  * Wesley Terpstra
  * Paul Walmsley
+ * Zong Li
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,475 +14,48 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * The FU540 PRCI implements clock and reset control for the SiFive
- * FU540-C000 chip.  This driver assumes that it has sole control
- * over all PRCI resources.
- *
- * This driver is based on the PRCI driver written by Wesley Terpstra:
- * 
https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
- *
  * References:
  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
  */
 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-
-/*
- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
- * hfclk and rtcclk
- */
-#define EXPECTED_CLK_PARENT_COUNT  2
-
-/*
- * Register offsets and bitmasks
- */
-
-/* COREPLLCFG0 */
-#define PRCI_COREPLLCFG0_OFFSET0x4
-# define PRCI_COREPLLCFG0_DIVR_SHIFT   0
-# define PRCI_COREPLLCFG0_DIVR_MASK(0x3f << 
PRCI_COREPLLCFG0_DIVR_SHIFT)
-# define PRCI_COREPLLCFG0_DIVF_SHIFT   6
-# define PRCI_COREPLLCFG0_DIVF_MASK(0x1ff << 
PRCI_COREPLLCFG0_DIVF_SHIFT)
-# define PRCI_COREPLLCFG0_DIVQ_SHIFT   15
-# define PRCI_COREPLLCFG0_DIVQ_MASK(0x7 << 
PRCI_COREPLLCFG0_DIVQ_SHIFT)
-# define PRCI_COREPLLCFG0_RANGE_SHIFT  18
-# define PRCI_COREPLLCFG0_RANGE_MASK   (0x7 << 
PRCI_COREPLLCFG0_RANGE_SHIFT)
-# define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
-# define PRCI_COREPLLCFG0_BYPASS_MASK  (0x1 << 
PRCI_COREPLLCFG0_BYPASS_SHIFT)
-# define PRCI_COREPLLCFG0_FSE_SHIFT25
-# define PRCI_COREPLLCFG0_FSE_MASK (0x1 << 
PRCI_COREPLLCFG0_FSE_SHIFT)
-# define PRCI_COREPLLCFG0_LOCK_SHIFT   31
-# define PRCI_COREPLLCFG0_LOCK_MASK(0x1 << 
PRCI_COREPLLCFG0_LOCK_SHIFT)
-
-/* DDRPLLCFG0 */
-#define PRCI_DDRPLLCFG0_OFFSET 0xc
-# define PRCI_DDRPLLCFG0_DIVR_SHIFT0
-# define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << 
PRCI_DDRPLLCFG0_DIVR_SHIFT)
-# define PRCI_DDRPLLCFG0_DIVF_SHIFT6
-# define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << 
PRCI_DDRPLLCFG0_DIVF_SHIFT)
-# define PRCI_DDRPLLCFG0_DIVQ_SHIFT15
-# define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << 
PRCI_DDRPLLCFG0_DIVQ_SHIFT)
-# define PRCI_DDRPLLCFG0_RANGE_SHIFT   18
-# define PRCI_DDRPLLCFG0_RANGE_MASK(0x7 << 
PRCI_DDRPLLCFG0_RANGE_SHIFT)
-# define PRCI_DDRPLLCFG0_BYPASS_SHIFT  24
-# define PRCI_DDRPLLCFG0_BYPASS_MASK   (0x1 << 
PRCI_DDRPLLCFG0_BYPASS_SHIFT)
-# define PRCI_DDRPLLCFG0_FSE_SHIFT 25
-# define PRCI_DDRPLLCFG0_FSE_MASK  (0x1 << 
PRCI_DDRPLLCFG0_FSE_SHIFT)
-# define PRCI_DDRPLLCFG0_LOCK_SHIFT31
-# define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << 
PRCI_DDRPLLCFG0_LOCK_SHIFT)
+#include "sifive-prci.h"
 
-/* DDRPLLCFG1 */
-#define PRCI_DDRPLLCFG1_OFFSET 0x10
-# define PRCI_DDRPLLCFG1_CKE_SHIFT 24
-# define PRCI_DDRPLLCFG1_CKE_MASK  (0x1 << 
PRCI_DDRPLLCFG1_CKE_SHIFT)
+/* PRCI integration data for each WRPLL instance */
 
-/* GEMGXLPLLCFG0 */