Re: [PATCH v3 1/3] dt-binding: gce: add gce header file for mt8192
Hi, Hsin-Yi: Hsin-Yi Wang 於 2021年2月5日 週五 下午3:19寫道： > > From: Yongqiang Niu > > Add documentation for the mt8192 gce. > > Add gce header file defined the gce hardware event, > subsys number and constant for mt8192. > > Signed-off-by: Yongqiang Niu > Reviewed-by: Rob Herring > Signed-off-by: Hsin-Yi Wang > --- > .../devicetree/bindings/mailbox/mtk-gce.txt | 7 +- > include/dt-bindings/gce/mt8192-gce.h | 419 ++ > 2 files changed, 423 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/gce/mt8192-gce.h > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index 7771ecaac5868..ac4245050d17d 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -9,8 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please > refer to > mailbox.txt for generic information about mailbox device-tree bindings. > > Required properties: > -- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or > - "mediatek,mt6779-gce". > +- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", > + "mediatek,mt8192-gce" or "mediatek,mt6779-gce". > - reg: Address range of the GCE unit > - interrupts: The interrupt signal from the GCE block > - clock: Clocks according to the common clock binding > @@ -36,7 +36,8 @@ Optional properties for a client device: >size: the total size of register address that GCE can access. > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', > -'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as > +'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h' or > +'dt-bindings/gce/mt6779-gce.h'. Such as > sub-system ids, thread priority, event ids. > > Example: > diff --git a/include/dt-bindings/gce/mt8192-gce.h > b/include/dt-bindings/gce/mt8192-gce.h > new file mode 100644 > index 0..062754416bfda > --- /dev/null > +++ b/include/dt-bindings/gce/mt8192-gce.h > @@ -0,0 +1,419 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2020 MediaTek Inc. > + * Author: Yongqiang Niu > + */ > + > +#ifndef _DT_BINDINGS_GCE_MT8192_H > +#define _DT_BINDINGS_GCE_MT8192_H > + > +/* assign timeout 0 also means default */ > +#define CMDQ_NO_TIMEOUT0x > +#define CMDQ_TIMEOUT_DEFAULT 1000 > + > +/* GCE thread priority */ > +#define CMDQ_THR_PRIO_LOWEST 0 > +#define CMDQ_THR_PRIO_11 > +#define CMDQ_THR_PRIO_22 > +#define CMDQ_THR_PRIO_33 > +#define CMDQ_THR_PRIO_44 > +#define CMDQ_THR_PRIO_55 > +#define CMDQ_THR_PRIO_66 > +#define CMDQ_THR_PRIO_HIGHEST 7 > + > +/* CPR count in 32bit register */ > +#define GCE_CPR_COUNT 1312 > + > +/* GCE subsys table */ > +#define SUBSYS_13000 > +#define SUBSYS_14001 > +#define SUBSYS_14012 > +#define SUBSYS_14023 > +#define SUBSYS_15024 > +#define SUBSYS_18805 > +#define SUBSYS_18816 > +#define SUBSYS_18827 > +#define SUBSYS_18838 > +#define SUBSYS_18849 > +#define SUBSYS_100010 > +#define SUBSYS_100111 > +#define SUBSYS_100212 > +#define SUBSYS_100313 > +#define SUBSYS_100414 > +#define SUBSYS_100515 > +#define SUBSYS_102016 > +#define SUBSYS_102817 > +#define SUBSYS_170018 > +#define SUBSYS_170119 > +#define SUBSYS_170220 > +#define SUBSYS_170321 > +#define SUBSYS_180022 > +#define SUBSYS_180123 > +#define SUBSYS_180224 > +#define SUBSYS_180425 > +#define SUBSYS_180526 > +#define SUBSYS_180827 > +#define SUBSYS_180a28 > +#define SUBSYS_180b29 > +#define SUBSYS_NO_SUPPORT 99 Why define no support? > + > +/* GCE General Purpose Register (GPR) support > + * Leave note for scenario usage here > + */ > +/* GCE: write mask */ > +#define GCE_GPR_R000x00 > +#define GCE_GPR_R010x01 > +/* MDP: P1: JPEG dest */ > +#define GCE_GPR_R020x02 > +#define GCE_GPR_R030x03 > +/* MDP: PQ color */ > +#define GCE_GPR_R040x04 > +/* MDP: 2D sharpness */ > +#define GCE_GPR_R050x05 > +/* DISP: poll esd */ > +#define GCE_GPR_R060x06 > +#define GCE_GPR_R070x07 > +/* MDP: P4: 2D sharpness dst */ > +#define GCE_GPR_R080x08 > +#define GCE_GPR_R090x09 > +/*
[PATCH v3 1/3] dt-binding: gce: add gce header file for mt8192
From: Yongqiang Niu Add documentation for the mt8192 gce. Add gce header file defined the gce hardware event, subsys number and constant for mt8192. Signed-off-by: Yongqiang Niu Reviewed-by: Rob Herring Signed-off-by: Hsin-Yi Wang --- .../devicetree/bindings/mailbox/mtk-gce.txt | 7 +- include/dt-bindings/gce/mt8192-gce.h | 419 ++ 2 files changed, 423 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/gce/mt8192-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 7771ecaac5868..ac4245050d17d 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -9,8 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to mailbox.txt for generic information about mailbox device-tree bindings. Required properties: -- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or - "mediatek,mt6779-gce". +- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", + "mediatek,mt8192-gce" or "mediatek,mt6779-gce". - reg: Address range of the GCE unit - interrupts: The interrupt signal from the GCE block - clock: Clocks according to the common clock binding @@ -36,7 +36,8 @@ Optional properties for a client device: size: the total size of register address that GCE can access. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', -'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as +'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h' or +'dt-bindings/gce/mt6779-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/include/dt-bindings/gce/mt8192-gce.h b/include/dt-bindings/gce/mt8192-gce.h new file mode 100644 index 0..062754416bfda --- /dev/null +++ b/include/dt-bindings/gce/mt8192-gce.h @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yongqiang Niu + */ + +#ifndef _DT_BINDINGS_GCE_MT8192_H +#define _DT_BINDINGS_GCE_MT8192_H + +/* assign timeout 0 also means default */ +#define CMDQ_NO_TIMEOUT0x +#define CMDQ_TIMEOUT_DEFAULT 1000 + +/* GCE thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_11 +#define CMDQ_THR_PRIO_22 +#define CMDQ_THR_PRIO_33 +#define CMDQ_THR_PRIO_44 +#define CMDQ_THR_PRIO_55 +#define CMDQ_THR_PRIO_66 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* CPR count in 32bit register */ +#define GCE_CPR_COUNT 1312 + +/* GCE subsys table */ +#define SUBSYS_13000 +#define SUBSYS_14001 +#define SUBSYS_14012 +#define SUBSYS_14023 +#define SUBSYS_15024 +#define SUBSYS_18805 +#define SUBSYS_18816 +#define SUBSYS_18827 +#define SUBSYS_18838 +#define SUBSYS_18849 +#define SUBSYS_100010 +#define SUBSYS_100111 +#define SUBSYS_100212 +#define SUBSYS_100313 +#define SUBSYS_100414 +#define SUBSYS_100515 +#define SUBSYS_102016 +#define SUBSYS_102817 +#define SUBSYS_170018 +#define SUBSYS_170119 +#define SUBSYS_170220 +#define SUBSYS_170321 +#define SUBSYS_180022 +#define SUBSYS_180123 +#define SUBSYS_180224 +#define SUBSYS_180425 +#define SUBSYS_180526 +#define SUBSYS_180827 +#define SUBSYS_180a28 +#define SUBSYS_180b29 +#define SUBSYS_NO_SUPPORT 99 + +/* GCE General Purpose Register (GPR) support + * Leave note for scenario usage here + */ +/* GCE: write mask */ +#define GCE_GPR_R000x00 +#define GCE_GPR_R010x01 +/* MDP: P1: JPEG dest */ +#define GCE_GPR_R020x02 +#define GCE_GPR_R030x03 +/* MDP: PQ color */ +#define GCE_GPR_R040x04 +/* MDP: 2D sharpness */ +#define GCE_GPR_R050x05 +/* DISP: poll esd */ +#define GCE_GPR_R060x06 +#define GCE_GPR_R070x07 +/* MDP: P4: 2D sharpness dst */ +#define GCE_GPR_R080x08 +#define GCE_GPR_R090x09 +/* VCU: poll with timeout for GPR timer */ +#define GCE_GPR_R100x0A +#define GCE_GPR_R110x0B +/* CMDQ: debug */ +#define GCE_GPR_R120x0C +#define GCE_GPR_R130x0D +/* CMDQ: P7: debug */ +#define GCE_GPR_R140x0E +#define GCE_GPR_R150x0F + +#define
