Re: [PATCH v3 1/3] dt-bindings: clk: Update Stingray binding doc
Quoting Ray Jui (2018-06-01 17:56:06) > From: Pramod Kumar > > Update Stingray clock binding document to add additional clock entries > with names matching the latest ASIC datasheet. Also modify a few existing > entries to make their naming more consistent with the rest of the entries > > Signed-off-by: Pramod Kumar > Signed-off-by: Ray Jui > --- Applied to clk-next
Re: [PATCH v3 1/3] dt-bindings: clk: Update Stingray binding doc
Quoting Ray Jui (2018-06-01 17:56:06) > From: Pramod Kumar > > Update Stingray clock binding document to add additional clock entries > with names matching the latest ASIC datasheet. Also modify a few existing > entries to make their naming more consistent with the rest of the entries > > Signed-off-by: Pramod Kumar > Signed-off-by: Ray Jui > --- Applied to clk-next
[PATCH v3 1/3] dt-bindings: clk: Update Stingray binding doc
From: Pramod Kumar Update Stingray clock binding document to add additional clock entries with names matching the latest ASIC datasheet. Also modify a few existing entries to make their naming more consistent with the rest of the entries Signed-off-by: Pramod Kumar Signed-off-by: Ray Jui --- .../bindings/clock/brcm,iproc-clocks.txt | 26 -- include/dt-bindings/clock/bcm-sr.h | 24 ++-- 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index f8e4a93..ab730ea 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -276,36 +276,38 @@ These clock IDs are defined in: clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK -clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH +clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK +clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK genpll3crystal 0 BCM_SR_GENPLL3 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK genpll4crystal 0 BCM_SR_GENPLL4 -ccngenpll4 1 BCM_SR_GENPLL4_CCN_CLK +clk_ccngenpll4 1 BCM_SR_GENPLL4_CCN_CLK clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK -noc_clkgenpll4 3 BCM_SR_GENPLL4_NOC_CLK +clk_nocgenpll4 3 BCM_SR_GENPLL4_NOC_CLK clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - genpll5crystal 0 BCM_SR_GENPLL5 -fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK -crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK -raid_ae_clkgenpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK +clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK +clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK +clk_raid_aegenpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK genpll6crystal 0 BCM_SR_GENPLL6 -48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK +clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK lcpll0 crystal 0 BCM_SR_LCPLL0 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK -clk_usb_reflcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK -sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK +clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK +clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK lcpll1 crystal 0 BCM_SR_LCPLL1 -wanlcpll1 1 BCM_SR_LCPLL0_WAN_CLK +clk_wanlcpll1 1 BCM_SR_LCPLL1_WAN_CLK +clk_usb_reflcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK +clk_crmu_tslcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE -pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK +clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h index cff6c6f..419011b 100644 --- a/include/dt-bindings/clock/bcm-sr.h +++ b/include/dt-bindings/clock/bcm-sr.h @@ -35,7 +35,7 @@ /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ #define BCM_SR_GENPLL0 0 -#define BCM_SR_GENPLL0_SATA_CLK1 +#define BCM_SR_GENPLL0_125M_CLK1 #define BCM_SR_GENPLL0_SCR_CLK 2 #define BCM_SR_GENPLL0_250M_CLK3 #define BCM_SR_GENPLL0_PCIE_AXI_CLK4 @@ -50,9 +50,11 @@ /* GENPLL 2 clock channel ID NITRO MHB*/ #define BCM_SR_GENPLL2 0 #define BCM_SR_GENPLL2_NIC_CLK 1 -#define BCM_SR_GENPLL2_250_NITRO_CLK 2 +#define BCM_SR_GENPLL2_TS_500_CLK 2 #define BCM_SR_GENPLL2_125_NITRO_CLK 3 #define BCM_SR_GENPLL2_CHIMP_CLK 4 +#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 +#define BCM_SR_GENPLL2_FS4_CLK 6 /* GENPLL 3 HSLS clock channel ID */ #define BCM_SR_GENPLL3
[PATCH v3 1/3] dt-bindings: clk: Update Stingray binding doc
From: Pramod Kumar Update Stingray clock binding document to add additional clock entries with names matching the latest ASIC datasheet. Also modify a few existing entries to make their naming more consistent with the rest of the entries Signed-off-by: Pramod Kumar Signed-off-by: Ray Jui --- .../bindings/clock/brcm,iproc-clocks.txt | 26 -- include/dt-bindings/clock/bcm-sr.h | 24 ++-- 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index f8e4a93..ab730ea 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -276,36 +276,38 @@ These clock IDs are defined in: clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK -clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH +clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK +clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK genpll3crystal 0 BCM_SR_GENPLL3 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK genpll4crystal 0 BCM_SR_GENPLL4 -ccngenpll4 1 BCM_SR_GENPLL4_CCN_CLK +clk_ccngenpll4 1 BCM_SR_GENPLL4_CCN_CLK clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK -noc_clkgenpll4 3 BCM_SR_GENPLL4_NOC_CLK +clk_nocgenpll4 3 BCM_SR_GENPLL4_NOC_CLK clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - genpll5crystal 0 BCM_SR_GENPLL5 -fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK -crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK -raid_ae_clkgenpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK +clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK +clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK +clk_raid_aegenpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK genpll6crystal 0 BCM_SR_GENPLL6 -48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK +clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK lcpll0 crystal 0 BCM_SR_LCPLL0 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK -clk_usb_reflcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK -sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK +clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK +clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK lcpll1 crystal 0 BCM_SR_LCPLL1 -wanlcpll1 1 BCM_SR_LCPLL0_WAN_CLK +clk_wanlcpll1 1 BCM_SR_LCPLL1_WAN_CLK +clk_usb_reflcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK +clk_crmu_tslcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE -pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK +clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h index cff6c6f..419011b 100644 --- a/include/dt-bindings/clock/bcm-sr.h +++ b/include/dt-bindings/clock/bcm-sr.h @@ -35,7 +35,7 @@ /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ #define BCM_SR_GENPLL0 0 -#define BCM_SR_GENPLL0_SATA_CLK1 +#define BCM_SR_GENPLL0_125M_CLK1 #define BCM_SR_GENPLL0_SCR_CLK 2 #define BCM_SR_GENPLL0_250M_CLK3 #define BCM_SR_GENPLL0_PCIE_AXI_CLK4 @@ -50,9 +50,11 @@ /* GENPLL 2 clock channel ID NITRO MHB*/ #define BCM_SR_GENPLL2 0 #define BCM_SR_GENPLL2_NIC_CLK 1 -#define BCM_SR_GENPLL2_250_NITRO_CLK 2 +#define BCM_SR_GENPLL2_TS_500_CLK 2 #define BCM_SR_GENPLL2_125_NITRO_CLK 3 #define BCM_SR_GENPLL2_CHIMP_CLK 4 +#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 +#define BCM_SR_GENPLL2_FS4_CLK 6 /* GENPLL 3 HSLS clock channel ID */ #define BCM_SR_GENPLL3
