[PATCH v3 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-15 Thread Purna Chandra Mandal 
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.

Signed-off-by: Purna Chandra Mandal 
Cc: Mark Brown 

---

Changes in v3:
- drop sqi_map/unmap_transfer() for core provided one
- replace devm_request_irq() with request_irq() for fixing release order
- check return value of clk_prepare_enable()
- fix checking devm_ioremap_resource() return value

Changes in v2:
- update subject line of dt/binding patch reflecting style of subsystem.

 drivers/spi/Kconfig |   6 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-pic32-sqi.c | 768 
 3 files changed, 775 insertions(+)
 create mode 100644 drivers/spi/spi-pic32-sqi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8a8ff50..281ed5d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -442,6 +442,12 @@ config SPI_PIC32
help
  SPI driver for Microchip PIC32 SPI master controller.
 
+config SPI_PIC32_SQI
+   tristate "Microchip PIC32 Quad SPI driver"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for PIC32 Quad SPI controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06019ed..3c74d00 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
 obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
+obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o spi-pxa2xx-dma.o
diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c
new file mode 100644
index 000..b215347
--- /dev/null
+++ b/drivers/spi/spi-pic32-sqi.c
@@ -0,0 +1,768 @@
+/*
+ * PIC32 Quad SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SQI registers */
+#define PESQI_XIP_CONF1_REG0x00
+#define PESQI_XIP_CONF2_REG0x04
+#define PESQI_CONF_REG 0x08
+#define PESQI_CTRL_REG 0x0C
+#define PESQI_CLK_CTRL_REG 0x10
+#define PESQI_CMD_THRES_REG0x14
+#define PESQI_INT_THRES_REG0x18
+#define PESQI_INT_ENABLE_REG   0x1C
+#define PESQI_INT_STAT_REG 0x20
+#define PESQI_TX_DATA_REG  0x24
+#define PESQI_RX_DATA_REG  0x28
+#define PESQI_STAT1_REG0x2C
+#define PESQI_STAT2_REG0x30
+#define PESQI_BD_CTRL_REG  0x34
+#define PESQI_BD_CUR_ADDR_REG  0x38
+#define PESQI_BD_BASE_ADDR_REG 0x40
+#define PESQI_BD_STAT_REG  0x44
+#define PESQI_BD_POLL_CTRL_REG 0x48
+#define PESQI_BD_TX_DMA_STAT_REG   0x4C
+#define PESQI_BD_RX_DMA_STAT_REG   0x50
+#define PESQI_THRES_REG0x54
+#define PESQI_INT_SIGEN_REG0x58
+
+/* PESQI_CONF_REG fields */
+#define PESQI_MODE 0x7
+#define  PESQI_MODE_BOOT   0
+#define  PESQI_MODE_PIO1
+#define  PESQI_MODE_DMA2
+#define  PESQI_MODE_XIP3
+#define PESQI_MODE_SHIFT   0
+#define PESQI_CPHA BIT(3)
+#define PESQI_CPOL BIT(4)
+#define PESQI_LSBF BIT(5)
+#define PESQI_RXLATCH  BIT(7)
+#define PESQI_SERMODE  BIT(8)
+#define PESQI_WP_ENBIT(9)
+#define PESQI_HOLD_EN  BIT(10)
+#define PESQI_BURST_EN BIT(12)
+#define PESQI_CS_CTRL_HW   BIT(15)
+#define PESQI_SOFT_RESET   BIT(16)
+#define PESQI_LANES_SHIFT  20
+#define  PESQI_SINGLE_LANE 0
+#define  PESQI_DUAL_LANE   1
+#define  PESQI_QUAD_LANE   2
+#define PESQI_CSEN_SHIFT   24
+#define PESQI_EN   BIT(23)
+
+/* PESQI_CLK_CTRL_REG fields */
+#define PESQI_CLK_EN   BIT(0)
+#define PESQI_CLK_STABLE   BIT(1)
+#define PESQI_CLKDIV_SHIFT 8
+#define PESQI_CLKDIV   0xff
+
+/* PESQI_INT_THR/CMD_THR_REG */
+#define PESQI_TXTHR_MASK   0x1f

[PATCH v3 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.

2016-04-15 Thread Purna Chandra Mandal 
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.

Signed-off-by: Purna Chandra Mandal 
Cc: Mark Brown 

---

Changes in v3:
- drop sqi_map/unmap_transfer() for core provided one
- replace devm_request_irq() with request_irq() for fixing release order
- check return value of clk_prepare_enable()
- fix checking devm_ioremap_resource() return value

Changes in v2:
- update subject line of dt/binding patch reflecting style of subsystem.

 drivers/spi/Kconfig |   6 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-pic32-sqi.c | 768 
 3 files changed, 775 insertions(+)
 create mode 100644 drivers/spi/spi-pic32-sqi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8a8ff50..281ed5d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -442,6 +442,12 @@ config SPI_PIC32
help
  SPI driver for Microchip PIC32 SPI master controller.
 
+config SPI_PIC32_SQI
+   tristate "Microchip PIC32 Quad SPI driver"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for PIC32 Quad SPI controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06019ed..3c74d00 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
 obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
+obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o spi-pxa2xx-dma.o
diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c
new file mode 100644
index 000..b215347
--- /dev/null
+++ b/drivers/spi/spi-pic32-sqi.c
@@ -0,0 +1,768 @@
+/*
+ * PIC32 Quad SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SQI registers */
+#define PESQI_XIP_CONF1_REG0x00
+#define PESQI_XIP_CONF2_REG0x04
+#define PESQI_CONF_REG 0x08
+#define PESQI_CTRL_REG 0x0C
+#define PESQI_CLK_CTRL_REG 0x10
+#define PESQI_CMD_THRES_REG0x14
+#define PESQI_INT_THRES_REG0x18
+#define PESQI_INT_ENABLE_REG   0x1C
+#define PESQI_INT_STAT_REG 0x20
+#define PESQI_TX_DATA_REG  0x24
+#define PESQI_RX_DATA_REG  0x28
+#define PESQI_STAT1_REG0x2C
+#define PESQI_STAT2_REG0x30
+#define PESQI_BD_CTRL_REG  0x34
+#define PESQI_BD_CUR_ADDR_REG  0x38
+#define PESQI_BD_BASE_ADDR_REG 0x40
+#define PESQI_BD_STAT_REG  0x44
+#define PESQI_BD_POLL_CTRL_REG 0x48
+#define PESQI_BD_TX_DMA_STAT_REG   0x4C
+#define PESQI_BD_RX_DMA_STAT_REG   0x50
+#define PESQI_THRES_REG0x54
+#define PESQI_INT_SIGEN_REG0x58
+
+/* PESQI_CONF_REG fields */
+#define PESQI_MODE 0x7
+#define  PESQI_MODE_BOOT   0
+#define  PESQI_MODE_PIO1
+#define  PESQI_MODE_DMA2
+#define  PESQI_MODE_XIP3
+#define PESQI_MODE_SHIFT   0
+#define PESQI_CPHA BIT(3)
+#define PESQI_CPOL BIT(4)
+#define PESQI_LSBF BIT(5)
+#define PESQI_RXLATCH  BIT(7)
+#define PESQI_SERMODE  BIT(8)
+#define PESQI_WP_ENBIT(9)
+#define PESQI_HOLD_EN  BIT(10)
+#define PESQI_BURST_EN BIT(12)
+#define PESQI_CS_CTRL_HW   BIT(15)
+#define PESQI_SOFT_RESET   BIT(16)
+#define PESQI_LANES_SHIFT  20
+#define  PESQI_SINGLE_LANE 0
+#define  PESQI_DUAL_LANE   1
+#define  PESQI_QUAD_LANE   2
+#define PESQI_CSEN_SHIFT   24
+#define PESQI_EN   BIT(23)
+
+/* PESQI_CLK_CTRL_REG fields */
+#define PESQI_CLK_EN   BIT(0)
+#define PESQI_CLK_STABLE   BIT(1)
+#define PESQI_CLKDIV_SHIFT 8
+#define PESQI_CLKDIV   0xff
+
+/* PESQI_INT_THR/CMD_THR_REG */
+#define PESQI_TXTHR_MASK   0x1f
+#define PESQI_TXTHR_SHIFT  8
+#define PESQI_RXTHR_MASK   0x1f
+#define