Re: [PATCH v3 2/4] dt: Document Qualcomm APQ8084 pinctrl binding
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote: > Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin > controller inside the APQ8084. > > Acked-by: Bjorn Andersson Don't remember giving you this... But, with the s/sdc3/sdc2 below I think it looks good; so with that change you have my Acked-by Regards, Bjorn > Signed-off-by: Georgi Djakov > --- > .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 179 > > 1 file changed, 179 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt > > diff --git > a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt > new file mode 100644 > index 000..9d95700 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt > @@ -0,0 +1,179 @@ > +Qualcomm APQ8084 TLMM block > + > +This binding describes the Top Level Mode Multiplexer block found in the > +MSM8960 platform. > + > +- compatible: > + Usage: required > + Value type: > + Definition: must be "qcom,apq8084-pinctrl" > + > +- reg: > + Usage: required > + Value type: > + Definition: the base address and size of the TLMM register space. > + > +- interrupts: > + Usage: required > + Value type: > + Definition: should specify the TLMM summary IRQ. > + > +- interrupt-controller: > + Usage: required > + Value type: > + Definition: identifies this node as an interrupt controller > + > +- #interrupt-cells: > + Usage: required > + Value type: > + Definition: must be 2. Specifying the pin number and flags, as defined > + in > + > +- gpio-controller: > + Usage: required > + Value type: > + Definition: identifies this node as a gpio controller > + > +- #gpio-cells: > + Usage: required > + Value type: > + Definition: must be 2. Specifying the pin number and flags, as defined > + in > + > +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt > for > +a general description of GPIO and interrupt bindings. > + > +Please refer to pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices, including the meaning of the > +phrase "pin configuration node". > + > +The pin configuration nodes act as a container for an abitrary number of > +subnodes. Each of these subnodes represents some desired configuration for a > +pin, a group, or a list of pins or groups. This configuration can include the > +mux function to select on those pin(s)/group(s), and various pin > configuration > +parameters, such as pull-up, drive strength, etc. > + > + > +PIN CONFIGURATION NODES: > + > +The name of each subnode is not important; all subnodes should be enumerated > +and processed purely based on their content. > + > +Each subnode only affects those parameters that are explicitly listed. In > +other words, a subnode that lists a mux function but no pin configuration > +parameters implies no information about any pin configuration parameters. > +Similarly, a pin subnode that describes a pullup parameter implies no > +information about e.g. the mux function. > + > + > +The following generic properties as defined in pinctrl-bindings.txt are valid > +to specify in a pin configuration subnode: > + > +- pins: > + Usage: required > + Value type: > + Definition: List of gpio pins affected by the properties specified in > + this subnode. Valid pins are: > + gpio0-gpio146, > + sdc1_clk, > + sdc1_cmd, > + sdc1_data > + sdc3_clk, > + sdc3_cmd, > + sdc3_data These are supposed to be sdc2. > + > +- function: > + Usage: required > + Value type: > + Definition: Specify the alternative function to be configured for the > + specified pins. Functions are only valid for gpio pins. > + Valid values are: > + adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, > + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, > + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, > + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, > + blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, > + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, > + blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, > + blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, > + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, > + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, > + blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, > + cam_mclk3, cci_async, cci_async_in0,
[PATCH v3 2/4] dt: Document Qualcomm APQ8084 pinctrl binding
Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin controller inside the APQ8084. Acked-by: Bjorn Andersson Signed-off-by: Georgi Djakov --- .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 179 1 file changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt new file mode 100644 index 000..9d95700 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt @@ -0,0 +1,179 @@ +Qualcomm APQ8084 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSM8960 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,apq8084-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio146, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc3_clk, + sdc3_cmd, + sdc3_data + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, + blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, + blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, + cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i + gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio, + hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic, + ldo_en, ldo_update, mdp_vsync,
[PATCH v3 2/4] dt: Document Qualcomm APQ8084 pinctrl binding
Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin controller inside the APQ8084. Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com Signed-off-by: Georgi Djakov gdja...@mm-sol.com --- .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 179 1 file changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt new file mode 100644 index 000..9d95700 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt @@ -0,0 +1,179 @@ +Qualcomm APQ8084 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSM8960 platform. + +- compatible: + Usage: required + Value type: string + Definition: must be qcom,apq8084-pinctrl + +- reg: + Usage: required + Value type: prop-encoded-array + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: prop-encoded-array + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: none + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: u32 + Definition: must be 2. Specifying the pin number and flags, as defined + in dt-bindings/interrupt-controller/irq.h + +- gpio-controller: + Usage: required + Value type: none + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: u32 + Definition: must be 2. Specifying the pin number and flags, as defined + in dt-bindings/gpio/gpio.h + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase pin configuration node. + +The pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: string-array + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio146, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc3_clk, + sdc3_cmd, + sdc3_data + +- function: + Usage: required + Value type: string + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, + blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, + blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, + cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i + gp_mn,
Re: [PATCH v3 2/4] dt: Document Qualcomm APQ8084 pinctrl binding
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote: Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin controller inside the APQ8084. Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com Don't remember giving you this... But, with the s/sdc3/sdc2 below I think it looks good; so with that change you have my Acked-by Regards, Bjorn Signed-off-by: Georgi Djakov gdja...@mm-sol.com --- .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 179 1 file changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt new file mode 100644 index 000..9d95700 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt @@ -0,0 +1,179 @@ +Qualcomm APQ8084 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSM8960 platform. + +- compatible: + Usage: required + Value type: string + Definition: must be qcom,apq8084-pinctrl + +- reg: + Usage: required + Value type: prop-encoded-array + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: prop-encoded-array + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: none + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: u32 + Definition: must be 2. Specifying the pin number and flags, as defined + in dt-bindings/interrupt-controller/irq.h + +- gpio-controller: + Usage: required + Value type: none + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: u32 + Definition: must be 2. Specifying the pin number and flags, as defined + in dt-bindings/gpio/gpio.h + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase pin configuration node. + +The pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: string-array + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio146, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc3_clk, + sdc3_cmd, + sdc3_data These are supposed to be sdc2. + +- function: + Usage: required + Value type: string + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, + blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, + blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, +
