Re: [PATCH v3 3/4] arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node

2020-09-18 Thread Suman Anna 
On 9/18/20 10:38 AM, Grygorii Strashko wrote:
> Add DT node for The TI j7200 MCU SoC Gigabit Ethernet two ports Switch
> subsystem (MCU CPSW NUSS).

nit, %s/j7200/J7200/ on this patch and the next.

regards
Suman

> 
> Signed-off-by: Grygorii Strashko 
> Tested-by: Kishon Vijay Abraham I 
> ---
>  .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi  | 74 +++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 
> b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index 7ecdfdb46436..a994276a8b3d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -34,6 +34,20 @@
>   };
>   };
>  
> + mcu_conf: syscon@40f0 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x0 0x40f0 0x0 0x2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x40f0 0x2>;
> +
> + phy_gmii_sel: phy@4040 {
> + compatible = "ti,am654-phy-gmii-sel";
> + reg = <0x4040 0x4>;
> + #phy-cells = <1>;
> + };
> + };
> +
>   chipid@4314 {
>   compatible = "ti,am654-chipid";
>   reg = <0x00 0x4314 0x00 0x4>;
> @@ -136,4 +150,64 @@
>   ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
>   };
>   };
> +
> + mcu_cpsw: ethernet@4600 {
> + compatible = "ti,j721e-cpsw-nuss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x4600 0x0 0x20>;
> + reg-names = "cpsw_nuss";
> + ranges = <0x0 0x0 0x0 0x4600 0x0 0x20>;
> + dma-coherent;
> + clocks = <_clks 18 21>;
> + clock-names = "fck";
> + power-domains = <_pds 18 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <_udmap 0xf000>,
> +<_udmap 0xf001>,
> +<_udmap 0xf002>,
> +<_udmap 0xf003>,
> +<_udmap 0xf004>,
> +<_udmap 0xf005>,
> +<_udmap 0xf006>,
> +<_udmap 0xf007>,
> +<_udmap 0x7000>;
> + dma-names = "tx0", "tx1", "tx2", "tx3",
> + "tx4", "tx5", "tx6", "tx7",
> + "rx";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpsw_port1: port@1 {
> + reg = <1>;
> + ti,mac-only;
> + label = "port1";
> + ti,syscon-efuse = <_conf 0x200>;
> + phys = <_gmii_sel 1>;
> + };
> + };
> +
> + davinci_mdio: mdio@f00 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + reg = <0x0 0xf00 0x0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <_clks 18 21>;
> + clock-names = "fck";
> + bus_freq = <100>;
> + };
> +
> + cpts@3d000 {
> + compatible = "ti,am65-cpts";
> + reg = <0x0 0x3d000 0x0 0x400>;
> + clocks = <_clks 18 2>;
> + clock-names = "cpts";
> + interrupts-extended = < GIC_SPI 858 
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "cpts";
> + ti,cpts-ext-ts-inputs = <4>;
> + ti,cpts-periodic-outputs = <2>;
> + };
> + };
>  };
>

[PATCH v3 3/4] arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node

2020-09-18 Thread Grygorii Strashko 
Add DT node for The TI j7200 MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).

Signed-off-by: Grygorii Strashko 
Tested-by: Kishon Vijay Abraham I 
---
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi  | 74 +++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 
b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 7ecdfdb46436..a994276a8b3d 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -34,6 +34,20 @@
};
};
 
+   mcu_conf: syscon@40f0 {
+   compatible = "syscon", "simple-mfd";
+   reg = <0x0 0x40f0 0x0 0x2>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x0 0x0 0x40f0 0x2>;
+
+   phy_gmii_sel: phy@4040 {
+   compatible = "ti,am654-phy-gmii-sel";
+   reg = <0x4040 0x4>;
+   #phy-cells = <1>;
+   };
+   };
+
chipid@4314 {
compatible = "ti,am654-chipid";
reg = <0x00 0x4314 0x00 0x4>;
@@ -136,4 +150,64 @@
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
};
+
+   mcu_cpsw: ethernet@4600 {
+   compatible = "ti,j721e-cpsw-nuss";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   reg = <0x0 0x4600 0x0 0x20>;
+   reg-names = "cpsw_nuss";
+   ranges = <0x0 0x0 0x0 0x4600 0x0 0x20>;
+   dma-coherent;
+   clocks = <_clks 18 21>;
+   clock-names = "fck";
+   power-domains = <_pds 18 TI_SCI_PD_EXCLUSIVE>;
+
+   dmas = <_udmap 0xf000>,
+  <_udmap 0xf001>,
+  <_udmap 0xf002>,
+  <_udmap 0xf003>,
+  <_udmap 0xf004>,
+  <_udmap 0xf005>,
+  <_udmap 0xf006>,
+  <_udmap 0xf007>,
+  <_udmap 0x7000>;
+   dma-names = "tx0", "tx1", "tx2", "tx3",
+   "tx4", "tx5", "tx6", "tx7",
+   "rx";
+
+   ethernet-ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpsw_port1: port@1 {
+   reg = <1>;
+   ti,mac-only;
+   label = "port1";
+   ti,syscon-efuse = <_conf 0x200>;
+   phys = <_gmii_sel 1>;
+   };
+   };
+
+   davinci_mdio: mdio@f00 {
+   compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+   reg = <0x0 0xf00 0x0 0x100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <_clks 18 21>;
+   clock-names = "fck";
+   bus_freq = <100>;
+   };
+
+   cpts@3d000 {
+   compatible = "ti,am65-cpts";
+   reg = <0x0 0x3d000 0x0 0x400>;
+   clocks = <_clks 18 2>;
+   clock-names = "cpts";
+   interrupts-extended = < GIC_SPI 858 
IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "cpts";
+   ti,cpts-ext-ts-inputs = <4>;
+   ti,cpts-periodic-outputs = <2>;
+   };
+   };
 };
-- 
2.17.1