These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 dispcc bindings.
Signed-off-by: Jonathan Marek
---
...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 18 ++--
.../bindings/clock/qcom,sc7180-dispcc.yaml| 86 ---
2 files changed, 12 insertions(+), 92 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml =>
qcom,dispcc.yaml} (86%)
delete mode 100644
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
similarity index 86%
rename from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
rename to Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index ead44705333b..7d5b25dfe0b1 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
@@ -1,32 +1,37 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Display Clock & Reset Controller Binding for SDM845
+title: Qualcomm Display Clock & Reset Controller Binding
maintainers:
- Taniya Das
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains on SDM845.
+ power domains on SDM845/SC7180.
- See also dt-bindings/clock/qcom,dispcc-sdm845.h.
+ See also:
+dt-bindings/clock/qcom,dispcc-sdm845.h
+dt-bindings/clock/qcom,dispcc-sc7180.h
properties:
compatible:
-const: qcom,sdm845-dispcc
+enum:
+ - qcom,sdm845-dispcc
+ - qcom,sc7180-dispcc
# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
# The code had to use hardcoded mechanisms to find the input clocks.
# New dts files should have these clocks.
clocks:
+minItems: 8
items:
- description: Board XO source
- description: GPLL0 source from GCC
- - description: GPLL0 div source from GCC
+ - description: GPLL0 div source from GCC (sdm845 only)
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
@@ -35,6 +40,7 @@ properties:
- description: VCO DIV clock from DP PHY
clock-names:
+minItems: 8
items:
- const: bi_tcxo
- const: gcc_disp_gpll0_clk_src
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
deleted file mode 100644
index e94847f92770..
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
+++ /dev/null
@@ -1,86 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display Clock & Reset Controller Binding for SC7180
-
-maintainers:
- - Taniya Das
-
-description: |
- Qualcomm display clock control module which supports the clocks, resets and
- power domains on SC7180.
-
- See also dt-bindings/clock/qcom,dispcc-sc7180.h.
-
-properties:
- compatible:
-const: qcom,sc7180-dispcc
-
- clocks:
-items:
- - description: Board XO source
- - description: GPLL0 source from GCC
- - description: Byte clock from DSI PHY
- - description: Pixel clock from DSI PHY
- - description: Link clock from DP PHY
- - description: VCO DIV clock from DP PHY
-
- clock-names:
-items:
- - const: bi_tcxo
- - const: gcc_disp_gpll0_clk_src
- - const: dsi0_phy_pll_out_byteclk
- - const: dsi0_phy_pll_out_dsiclk
- - const: dp_phy_pll_link_clk
- - const: dp_phy_pll_vco_div_clk
-
- '#clock-cells':
-const: 1
-
- '#reset-cells':
-const: 1
-
- '#power-domain-cells':
-const: 1
-
- reg:
-maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
-#include
-#include
-clock-controller@af0 {
- compatible = "qcom,sc7180-dispcc";
- reg = <0x0af0 0x20>;
- clocks = < RPMH_CXO_CLK>,
- < GCC_DISP_GPLL0_CLK_SRC>,
- <_phy 0>,
- <_phy 1>,
- <_phy 0>,
- <_phy 1>;
- clock-names = "bi_tcxo",
-"gcc_disp_gpll0_clk_src",
-"dsi0_phy_pll_out_byteclk",
-"dsi0_phy_pll_out_dsiclk",
-"dp_phy_pll_link_clk",
-"dp_phy_pll_vco_div_clk";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells =
