Re: [PATCH v3 4/5] clk: rockchip: add pll up and down when change pll freq

[Stephen Boyd]

Quoting Elaine Zhang (2019-09-26 20:00:43)
> set pll sequence:
> ->set pll to slow mode or other plls
> ->set pll down
> ->set pll params
> ->set pll up
> ->wait pll lock status
> ->set pll to normal mode
> 
> To slove the system error:

solve?

> wait_pll_lock: timeout waiting for pll to lock
> pll_set_params: pll update unsucessful,
> trying to restore old params
> 

This commit text needs help. It looks like pseudo-code.

[PATCH v3 4/5] clk: rockchip: add pll up and down when change pll freq

[Elaine Zhang]

set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode

To slove the system error:
wait_pll_lock: timeout waiting for pll to lock
pll_set_params: pll update unsucessful,
trying to restore old params

Signed-off-by: Elaine Zhang 
---
 drivers/clk/rockchip/clk-pll.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 198417d56300..390e9473807a 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -199,6 +199,11 @@ static int rockchip_rk3036_pll_set_params(struct 
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
 
+   /* set pll power down */
+   writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
+RK3036_PLLCON1_PWRDOWN, 0),
+  pll->reg_base + RK3036_PLLCON(1));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
  RK3036_PLLCON0_FBDIV_SHIFT) |
@@ -220,6 +225,11 @@ static int rockchip_rk3036_pll_set_params(struct 
rockchip_clk_pll *pll,
pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 
+   /* set pll power up */
+   writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
+  pll->reg_base + RK3036_PLLCON(1));
+   udelay(1);
+
/* wait for the pll to lock */
ret = rockchip_pll_wait_lock(pll);
if (ret) {
@@ -676,6 +686,11 @@ static int rockchip_rk3399_pll_set_params(struct 
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
 
+   /* set pll power down */
+   writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
+RK3399_PLLCON3_PWRDOWN, 0),
+  pll->reg_base + RK3399_PLLCON(3));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
  RK3399_PLLCON0_FBDIV_SHIFT),
@@ -699,6 +714,12 @@ static int rockchip_rk3399_pll_set_params(struct 
rockchip_clk_pll *pll,
RK3399_PLLCON3_DSMPD_SHIFT),
   pll->reg_base + RK3399_PLLCON(3));
 
+   /* set pll power up */
+   writel(HIWORD_UPDATE(0,
+RK3399_PLLCON3_PWRDOWN, 0),
+  pll->reg_base + RK3399_PLLCON(3));
+   udelay(1);
+
/* wait for the pll to lock */
ret = rockchip_rk3399_pll_wait_lock(pll);
if (ret) {
-- 
1.9.1