Re: [PATCH v3 4/6] dt-bindings: clock: Add support for the MSM8998 mmcc

2019-04-30 Thread Bjorn Andersson
On Tue 30 Apr 19:26 PDT 2019, Jeffrey Hugo wrote:

> Document the multimedia clock controller found on MSM8998.
> 
> Signed-off-by: Jeffrey Hugo 
> Reviewed-by: Rob Herring 

Reviewed-by: Bjorn Andersson 

> ---
>  .../devicetree/bindings/clock/qcom,mmcc.txt|  21 +++
>  include/dt-bindings/clock/qcom,mmcc-msm8998.h  | 210 
> +
>  2 files changed, 231 insertions(+)
>  create mode 100644 include/dt-bindings/clock/qcom,mmcc-msm8998.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt 
> b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
> index 8b0f784..a92f3cb 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
> @@ -10,11 +10,32 @@ Required properties :
>   "qcom,mmcc-msm8960"
>   "qcom,mmcc-msm8974"
>   "qcom,mmcc-msm8996"
> + "qcom,mmcc-msm8998"
>  
>  - reg : shall contain base register location and length
>  - #clock-cells : shall contain 1
>  - #reset-cells : shall contain 1
>  
> +For MSM8998 only:
> + - clocks: a list of phandles and clock-specifier pairs,
> +   one for each entry in clock-names.
> + - clock-names: "xo" for the xo clock.
> +"gpll0" for the global pll 0 clock.
> +"dsi0dsi" for the dsi0 pll dsi clock (required if dsi is
> + enabled, optional otherwise).
> +"dsi0byte" for the dsi0 pll byte clock (required if dsi
> + is enabled, optional otherwise).
> +"dsi1dsi" for the dsi1 pll dsi clock (required if dsi is
> + enabled, optional otherwise).
> +"dsi1byte" for the dsi1 pll byte clock (required if dsi
> + is enabled, optional otherwise).
> +"hdmipll" for the hdmi pll clock (required if hdmi is
> + enabled, optional otherwise).
> +"dpvco" for the displayport pll vco clock (required if
> + dp is enabled, optional otherwise).
> +"dplink" for the displayport pll link clock (required if
> + dp is enabled, optional otherwise).
> +
>  Optional properties :
>  - #power-domain-cells : shall contain 1
>  
> diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8998.h 
> b/include/dt-bindings/clock/qcom,mmcc-msm8998.h
> new file mode 100644
> index 000..ecbafdb
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,mmcc-msm8998.h
> @@ -0,0 +1,210 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
> +#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
> +
> +#define MMPLL0   0
> +#define MMPLL0_OUT_EVEN  1
> +#define MMPLL1   2
> +#define MMPLL1_OUT_EVEN  3
> +#define MMPLL3   4
> +#define MMPLL3_OUT_EVEN  5
> +#define MMPLL4   6
> +#define MMPLL4_OUT_EVEN  7
> +#define MMPLL5   8
> +#define MMPLL5_OUT_EVEN  9
> +#define MMPLL6   10
> +#define MMPLL6_OUT_EVEN  11
> +#define MMPLL7   12
> +#define MMPLL7_OUT_EVEN  13
> +#define MMPLL10  14
> +#define MMPLL10_OUT_EVEN 15
> +#define BYTE0_CLK_SRC16
> +#define BYTE1_CLK_SRC17
> +#define CCI_CLK_SRC  18
> +#define CPP_CLK_SRC  19
> +#define CSI0_CLK_SRC 20
> +#define CSI1_CLK_SRC 21
> +#define CSI2_CLK_SRC 22
> +#define CSI3_CLK_SRC 23
> +#define CSIPHY_CLK_SRC   24
> +#define CSI0PHYTIMER_CLK_SRC 25
> +#define CSI1PHYTIMER_CLK_SRC 26
> +#define CSI2PHYTIMER_CLK_SRC 27
> +#define DP_AUX_CLK_SRC   28
> +#define DP_CRYPTO_CLK_SRC29
> +#define DP_LINK_CLK_SRC  30
> +#define DP_PIXEL_CLK_SRC 31
> +#define ESC0_CLK_SRC   

[PATCH v3 4/6] dt-bindings: clock: Add support for the MSM8998 mmcc

2019-04-30 Thread Jeffrey Hugo
Document the multimedia clock controller found on MSM8998.

Signed-off-by: Jeffrey Hugo 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/clock/qcom,mmcc.txt|  21 +++
 include/dt-bindings/clock/qcom,mmcc-msm8998.h  | 210 +
 2 files changed, 231 insertions(+)
 create mode 100644 include/dt-bindings/clock/qcom,mmcc-msm8998.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 8b0f784..a92f3cb 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -10,11 +10,32 @@ Required properties :
"qcom,mmcc-msm8960"
"qcom,mmcc-msm8974"
"qcom,mmcc-msm8996"
+   "qcom,mmcc-msm8998"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
 - #reset-cells : shall contain 1
 
+For MSM8998 only:
+   - clocks: a list of phandles and clock-specifier pairs,
+ one for each entry in clock-names.
+   - clock-names: "xo" for the xo clock.
+  "gpll0" for the global pll 0 clock.
+  "dsi0dsi" for the dsi0 pll dsi clock (required if dsi is
+   enabled, optional otherwise).
+  "dsi0byte" for the dsi0 pll byte clock (required if dsi
+   is enabled, optional otherwise).
+  "dsi1dsi" for the dsi1 pll dsi clock (required if dsi is
+   enabled, optional otherwise).
+  "dsi1byte" for the dsi1 pll byte clock (required if dsi
+   is enabled, optional otherwise).
+  "hdmipll" for the hdmi pll clock (required if hdmi is
+   enabled, optional otherwise).
+  "dpvco" for the displayport pll vco clock (required if
+   dp is enabled, optional otherwise).
+  "dplink" for the displayport pll link clock (required if
+   dp is enabled, optional otherwise).
+
 Optional properties :
 - #power-domain-cells : shall contain 1
 
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8998.h 
b/include/dt-bindings/clock/qcom,mmcc-msm8998.h
new file mode 100644
index 000..ecbafdb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8998.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
+
+#define MMPLL0 0
+#define MMPLL0_OUT_EVEN1
+#define MMPLL1 2
+#define MMPLL1_OUT_EVEN3
+#define MMPLL3 4
+#define MMPLL3_OUT_EVEN5
+#define MMPLL4 6
+#define MMPLL4_OUT_EVEN7
+#define MMPLL5 8
+#define MMPLL5_OUT_EVEN9
+#define MMPLL6 10
+#define MMPLL6_OUT_EVEN11
+#define MMPLL7 12
+#define MMPLL7_OUT_EVEN13
+#define MMPLL1014
+#define MMPLL10_OUT_EVEN   15
+#define BYTE0_CLK_SRC  16
+#define BYTE1_CLK_SRC  17
+#define CCI_CLK_SRC18
+#define CPP_CLK_SRC19
+#define CSI0_CLK_SRC   20
+#define CSI1_CLK_SRC   21
+#define CSI2_CLK_SRC   22
+#define CSI3_CLK_SRC   23
+#define CSIPHY_CLK_SRC 24
+#define CSI0PHYTIMER_CLK_SRC   25
+#define CSI1PHYTIMER_CLK_SRC   26
+#define CSI2PHYTIMER_CLK_SRC   27
+#define DP_AUX_CLK_SRC 28
+#define DP_CRYPTO_CLK_SRC  29
+#define DP_LINK_CLK_SRC30
+#define DP_PIXEL_CLK_SRC   31
+#define ESC0_CLK_SRC   32
+#define ESC1_CLK_SRC   33
+#define EXTPCLK_CLK_SRC34
+#define FD_CORE_CLK_SRC35
+#define HDMI_CLK_SRC