Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
On 9/24/20 2:16 AM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-23 09:10:04)
On 9/22/20 3:00 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:07)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
[...]
+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+ { .fw_name = "bi_tcxo" },
+ { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+ { .fw_name = "dsi1_phy_pll_out_dsiclk" },
Can we remove clk postfix on these clk names?
This is consistent with the names used in both sdm845 and sc7180
drivers. If this should change then those should be changed too?
If DT isn't using it already then it sounds OK to change the other
SoCs. Otherwise fix it just for this one.
Both sdm845 and sc7180 DT are using these names. I kept these names in
the V4 I just sent, keeping things consistent is a lot more beneficial
than dropping 3 extra characters from the DT names.
The sc7180 dispcc driver is recent and has all of these:
- dp_phy_pll_link_clk
- dp_phy_pll_vco_div_clk
- dsi0_phy_pll_out_byteclk
- dsi0_phy_pll_out_dsiclk
So I just can't imagine dropping the clk postfix is actually important.
Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
Quoting Jonathan Marek (2020-09-23 09:10:04)
> On 9/22/20 3:00 PM, Stephen Boyd wrote:
> > Quoting Jonathan Marek (2020-09-11 08:34:07)
> >> diff --git a/drivers/clk/qcom/dispcc-sm8250.c
> >> b/drivers/clk/qcom/dispcc-sm8250.c
> >> new file mode 100644
> >> index ..7c0f384a3a42
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/dispcc-sm8250.c
> >> @@ -0,0 +1,1100 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
> >> + */
> >> +
> > [...]
> >> +
> >> +static const struct clk_parent_data disp_cc_parent_data_6[] = {
> >> + { .fw_name = "bi_tcxo" },
> >> + { .fw_name = "dsi0_phy_pll_out_dsiclk" },
> >> + { .fw_name = "dsi1_phy_pll_out_dsiclk" },
> >
> > Can we remove clk postfix on these clk names?
> >
>
> This is consistent with the names used in both sdm845 and sc7180
> drivers. If this should change then those should be changed too?
If DT isn't using it already then it sounds OK to change the other
SoCs. Otherwise fix it just for this one.
Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
On 9/22/20 3:00 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:07)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
[...]
+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+ { .fw_name = "bi_tcxo" },
+ { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+ { .fw_name = "dsi1_phy_pll_out_dsiclk" },
Can we remove clk postfix on these clk names?
This is consistent with the names used in both sdm845 and sc7180
drivers. If this should change then those should be changed too?
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
+ F(1920, P_BI_TCXO, 1, 0, 0),
+ F(3750, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
+ F(7500, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
+ .cmd_rcgr = 0x22bc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_3,
+ .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_ahb_clk_src",
+ .parent_data = disp_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
+ F(1920, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+ .cmd_rcgr = 0x2110,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_byte0_clk_src",
+ .parent_data = disp_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
Why do we need CLK_GET_RATE_NOCACHE? Please remove it.
+ .ops = _byte2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+ .cmd_rcgr = 0x212c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_byte1_clk_src",
+ .parent_data = disp_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .ops = _byte2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
+ .cmd_rcgr = 0x2240,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_1,
+ .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_dp_aux1_clk_src",
+ .parent_data = disp_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
+ .cmd_rcgr = 0x21dc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_1,
+ .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_dp_aux_clk_src",
+ .parent_data = disp_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
+ F(16200, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(27000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(54000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(81000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
+ .cmd_rcgr = 0x220c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_0,
+ .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_dp_link1_clk_src",
+ .parent_data = disp_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .ops = _rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
+ .cmd_rcgr = 0x2178,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_0,
+
Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
Quoting Jonathan Marek (2020-09-11 08:34:07)
> diff --git a/drivers/clk/qcom/dispcc-sm8250.c
> b/drivers/clk/qcom/dispcc-sm8250.c
> new file mode 100644
> index ..7c0f384a3a42
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-sm8250.c
> @@ -0,0 +1,1100 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
> + */
> +
[...]
> +
> +static const struct clk_parent_data disp_cc_parent_data_6[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "dsi0_phy_pll_out_dsiclk" },
> + { .fw_name = "dsi1_phy_pll_out_dsiclk" },
Can we remove clk postfix on these clk names?
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
> + F(1920, P_BI_TCXO, 1, 0, 0),
> + F(3750, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
> + F(7500, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
> + .cmd_rcgr = 0x22bc,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_3,
> + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_ahb_clk_src",
> + .parent_data = disp_cc_parent_data_3,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = _rcg2_shared_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
> + F(1920, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
> + .cmd_rcgr = 0x2110,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_2,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_clk_src",
> + .parent_data = disp_cc_parent_data_2,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
Why do we need CLK_GET_RATE_NOCACHE? Please remove it.
> + .ops = _byte2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
> + .cmd_rcgr = 0x212c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_2,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte1_clk_src",
> + .parent_data = disp_cc_parent_data_2,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = _byte2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
> + .cmd_rcgr = 0x2240,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_aux1_clk_src",
> + .parent_data = disp_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = _rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
> + .cmd_rcgr = 0x21dc,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_aux_clk_src",
> + .parent_data = disp_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = _rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
> + F(16200, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + F(27000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + F(54000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + F(81000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
> + .cmd_rcgr = 0x220c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_0,
> + .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_link1_clk_src",
> + .parent_data = disp_cc_parent_data_0,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = _rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
> + .cmd_rcgr = 0x2178,
> + .mnd_width = 0,
>
[PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
Add support for the display clock controller found on SM8250
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1 +
drivers/clk/qcom/dispcc-sm8250.c | 1100 ++
3 files changed, 1110 insertions(+)
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index c15907842cb3..c81eae64b809 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -422,6 +422,15 @@ config SM_DISPCC_8150
Say Y if you want to support display devices and functionality such as
splash screen.
+config SM_DISPCC_8250
+ tristate "SM8250 Display Clock Controller"
+ select SM_GCC_8250
+ help
+ Support for the display clock controller on Qualcomm Technologies, Inc
+ SM8250 devices.
+ Say Y if you want to support display devices and functionality such as
+ splash screen.
+
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index edea87f1c7e6..8eb395d02a32 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o
+obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_CORE_BI_PLL_TEST_SE,
+ P_DISP_CC_PLL0_OUT_MAIN,
+ P_DISP_CC_PLL1_OUT_EVEN,
+ P_DISP_CC_PLL1_OUT_MAIN,
+ P_DP_PHY_PLL_LINK_CLK,
+ P_DP_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX1_PHY_PLL_LINK_CLK,
+ P_DPTX1_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX2_PHY_PLL_LINK_CLK,
+ P_DPTX2_PHY_PLL_VCO_DIV_CLK,
+ P_DSI0_PHY_PLL_OUT_BYTECLK,
+ P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_DSI1_PHY_PLL_OUT_BYTECLK,
+ P_DSI1_PHY_PLL_OUT_DSICLK,
+ P_EDP_PHY_PLL_LINK_CLK,
+ P_EDP_PHY_PLL_VCO_DIV_CLK,
+};
+
+static struct pll_vco lucid_vco[] = {
+ { 24960, 20, 0 },
+};
+
+static const struct alpha_pll_config disp_cc_pll0_config = {
+ .l = 0x47,
+ .alpha = 0xE000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_alpha_pll disp_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "disp_cc_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config disp_cc_pll1_config = {
+ .l = 0x1F,
+ .alpha = 0x4000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_alpha_pll disp_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "disp_cc_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct parent_map disp_cc_parent_map_0[] = {
+ {
