Re: [PATCH v4] RISC-V: enable XIP
On Sat, Mar 06, 2021 at 02:14:38PM +0200, Vitaly Wool wrote: > Introduce XIP (eXecute In Place) support for RISC-V platforms. > It allows code to be executed directly from non-volatile storage > directly addressable by the CPU, such as QSPI NOR flash which can > be found on many RISC-V platforms. This makes way for significant > optimization of RAM footprint. The XIP kernel is not compressed > since it has to run directly from flash, so it will occupy more > space on the non-volatile storage to The physical flash address > used to link the kernel object files and for storing it has to > be known at compile time and is represented by a Kconfig option. > > XIP on RISC-V will currently only work on MMU-enabled kernels. > > Signed-off-by: Vitaly Wool > --- The impact of this patch on RISC-V images running in qemu is quite fatal. [0.00] Linux version 5.12.0-rc3-next-20210319 (gro...@saturn.roeck-us.net) (riscv64-linux-gcc (GCC) 9.3.0, GNU ld (GNU Binutils) 2.34) #1 SMP Fri Mar 19 04:01:41 PDT 2021 [0.00] OF: fdt: Ignoring memory range 0x8000 - 0x8020 [0.00] Machine model: riscv-virtio,qemu [0.00] earlycon: uart8250 at MMIO 0x1000 (options '115200') [0.00] printk: bootconsole [uart8250] enabled [0.00] efi: UEFI not found. [0.00] Unable to handle kernel paging request at virtual address 4001 [0.00] Oops [#1] [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 5.12.0-rc3-next-20210319 #1 [0.00] Hardware name: riscv-virtio,qemu (DT) [0.00] epc : fdt_check_header+0x0/0x1fc [0.00] ra : early_init_dt_verify+0x16/0x6e [0.00] epc : ffe00049c04a ra : ffe000a26144 sp : ffe001603f10 [0.00] gp : ffe0017d04b0 tp : ffe001611280 t0 : [0.00] t1 : 12adc51a t2 : 0004ffeb s0 : ffe001603f30 [0.00] s1 : 4000 a0 : 4000 a1 : ffe001617ae8 [0.00] a2 : a3 : 0001 a4 : 0018 [0.00] a5 : ffe000c0f8f0 a6 : ffe01fdfee70 a7 : [0.00] s2 : 8200 s3 : 0fff s4 : ffe000c0ec60 [0.00] s5 : 0006 s6 : 01c0 s7 : ffe01fdfee40 [0.00] s8 : 81000200 s9 : 8200 s10: ffe000c01000 [0.00] s11: 0fff t3 : 000e t4 : a600 [0.00] t5 : t6 : 0015 [0.00] status: 0100 badaddr: 4001 cause: 000d [0.00] Call Trace: [0.00] [] fdt_check_header+0x0/0x1fc [0.00] [] setup_arch+0x3a8/0x414 [0.00] [] start_kernel+0x8e/0x62c [0.00] random: get_random_bytes called from print_oops_end_marker+0x22/0x44 with crng_init=0 [0.00] ---[ end trace ]--- [0.00] Kernel panic - not syncing: Attempted to kill the idle task! [0.00] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- This is with riscv:defconfig. Reverting this patch fixes the problem. Bisect log is attached. Guenter --- # bad: [f00397ee41c79b6155b9b44abd0055b2c0621349] Add linux-next specific files for 20210319 # good: [1e28eed17697bcf343c6743f0028cc3b5dd88bf0] Linux 5.12-rc3 git bisect start 'HEAD' 'v5.12-rc3' # bad: [728bc19f9c531acd94e4139e8258a1577f17d2ff] Merge remote-tracking branch 'drm/drm-next' git bisect bad 728bc19f9c531acd94e4139e8258a1577f17d2ff # bad: [ad5d10f254a7d91a9fadadcf2b109795544e9dcb] Merge remote-tracking branch 'hid/for-next' git bisect bad ad5d10f254a7d91a9fadadcf2b109795544e9dcb # good: [163518c802260a16b5bca8bd7fe0a9335a6860e1] Merge remote-tracking branch 'qcom/for-next' git bisect good 163518c802260a16b5bca8bd7fe0a9335a6860e1 # bad: [a9fdd30a39510f783a38fe5c30b2d888397b35d5] Merge remote-tracking branch 'btrfs/for-next' git bisect bad a9fdd30a39510f783a38fe5c30b2d888397b35d5 # good: [3f26d646c9c30116057e2cc34091e7d3fd894863] Merge remote-tracking branch 'microblaze/next' git bisect good 3f26d646c9c30116057e2cc34091e7d3fd894863 # good: [f0fd694b8c3eba5651fa9eed185cc1c39c1a3d64] Merge branch 'ext/qu/subpage-write-meta-v2' into for-next-next-v5.12-20210317 git bisect good f0fd694b8c3eba5651fa9eed185cc1c39c1a3d64 # bad: [762f6038cff9e5658c29936a0ff0398fb2b77dc9] Merge remote-tracking branch 'sh/for-next' git bisect bad 762f6038cff9e5658c29936a0ff0398fb2b77dc9 # good: [fb009cbdd0693bd633f11e99526617b3d392cfad] firmware: bcm47xx_nvram: rename finding function and its variables git bisect good fb009cbdd0693bd633f11e99526617b3d392cfad # good: [10b3a0a8f783dc5491921f0236f1b756cbe1b12d] Merge remote-tracking branch 'parisc-hd/for-next' git bisect good 10b3a0a8f783dc5491921f0236f1b756cbe1b12d # good: [2882b7626f4903a8e9250b328cdf7396a6deecac] sh: kernel: traps: remove unused variable git bis
Re: [PATCH v4] RISC-V: enable XIP
Hi Vitaly, I love your patch! Yet something to improve: [auto build test ERROR on linus/master] [also build test ERROR on v5.12-rc2] [cannot apply to linux/master] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Vitaly-Wool/RISC-V-enable-XIP/20210307-103904 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 280d542f6ffac0e6d65dc267f92191d509b13b64 config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/c9cb15092dcf53140fba57780677a9dcaef70612 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Vitaly-Wool/RISC-V-enable-XIP/20210307-103904 git checkout c9cb15092dcf53140fba57780677a9dcaef70612 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> riscv64-linux-ld: section .data LMA [0080,00a90eaf] >> overlaps section .text LMA [001095a0,014ae61b] >> riscv64-linux-ld: section .rodata VMA [ffe000cae640,ffe001042f0f] >> overlaps section .bss VMA [ffe00059d000,ffe001a54f6f] riscv64-linux-ld: arch/riscv/mm/init.o: in function `.L122': >> init.c:(.text+0x288): undefined reference to `__init_text_begin' riscv64-linux-ld: arch/riscv/mm/init.o: in function `.L123': >> init.c:(.text+0x290): undefined reference to `__init_data_begin' riscv64-linux-ld: arch/riscv/mm/init.o: in function `.L0 ': init.c:(.text+0x2ea): undefined reference to `__init_text_begin' >> riscv64-linux-ld: init.c:(.text+0x302): undefined reference to >> `__init_data_begin' --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip
Re: [PATCH v4] RISC-V: enable XIP
Hi Vitaly,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.12-rc2 next-20210305]
[cannot apply to linux/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Vitaly-Wool/RISC-V-enable-XIP/20210307-103904
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
280d542f6ffac0e6d65dc267f92191d509b13b64
config: riscv-defconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/c9cb15092dcf53140fba57780677a9dcaef70612
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Vitaly-Wool/RISC-V-enable-XIP/20210307-103904
git checkout c9cb15092dcf53140fba57780677a9dcaef70612
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross
ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
arch/riscv/kernel/cpu_ops_sbi.c: In function 'get_secondary_start_phys':
>> arch/riscv/kernel/cpu_ops_sbi.c:59:3: error: implicit declaration of
>> function 'XIP_PHYS_ADDR' [-Werror=implicit-function-declaration]
59 | XIP_PHYS_ADDR(secondary_start_sbi) :
| ^
cc1: some warnings being treated as errors
vim +/XIP_PHYS_ADDR +59 arch/riscv/kernel/cpu_ops_sbi.c
55
56 static inline unsigned long get_secondary_start_phys(void)
57 {
58 return IS_ENABLED(CONFIG_XIP_KERNEL) ?
> 59 XIP_PHYS_ADDR(secondary_start_sbi) :
60 __pa_symbol(secondary_start_sbi);
61 }
62
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
[PATCH v4] RISC-V: enable XIP
Introduce XIP (eXecute In Place) support for RISC-V platforms. It allows code to be executed directly from non-volatile storage directly addressable by the CPU, such as QSPI NOR flash which can be found on many RISC-V platforms. This makes way for significant optimization of RAM footprint. The XIP kernel is not compressed since it has to run directly from flash, so it will occupy more space on the non-volatile storage to The physical flash address used to link the kernel object files and for storing it has to be known at compile time and is represented by a Kconfig option. XIP on RISC-V will currently only work on MMU-enabled kernels. Signed-off-by: Vitaly Wool --- Changed in v2: - dedicated macro for XIP address fixup when MMU is not enabled yet = both for 32-bit and 64-bit RISC-V - SP is explicitly set to a safe place in RAM before __copy_data call - removed redundant alignment requirements in vmlinux-xip.lds.S - changed long -> uintptr_t typecast in __XIP_FIXUP macro. Changed in v3: - rebased against latest for-next - XIP address fixup macro now takes an argument - SMP related fixes Changes in v4: - rebased against the current for-next - less #ifdef's in C/ASM code - dedicated XIP_FIXUP_OFFSET assembler macro in head.S - C-specific definitions moved into #ifndef __ASSEMBLY__ - Fixed multi-core boot arch/riscv/Kconfig | 44 +- arch/riscv/Makefile | 8 +- arch/riscv/boot/Makefile| 13 +++ arch/riscv/include/asm/pgtable.h| 65 -- arch/riscv/kernel/cpu_ops_sbi.c | 10 ++- arch/riscv/kernel/head.S| 59 - arch/riscv/kernel/head.h| 3 + arch/riscv/kernel/setup.c | 8 +- arch/riscv/kernel/vmlinux-xip.lds.S | 132 arch/riscv/kernel/vmlinux.lds.S | 6 ++ arch/riscv/mm/init.c| 100 +++-- 11 files changed, 430 insertions(+), 18 deletions(-) create mode 100644 arch/riscv/kernel/vmlinux-xip.lds.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 85d626b8ce5e..59fb945a900e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -438,7 +438,7 @@ config EFI_STUB config EFI bool "UEFI runtime support" - depends on OF + depends on OF && !XIP_KERNEL select LIBFDT select UCS2_STRING select EFI_PARAMS_FROM_FDT @@ -462,11 +462,51 @@ config STACKPROTECTOR_PER_TASK def_bool y depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS +config XIP_KERNEL + bool "Kernel Execute-In-Place from ROM" + depends on MMU + help + Execute-In-Place allows the kernel to run from non-volatile storage + directly addressable by the CPU, such as NOR flash. This saves RAM + space since the text section of the kernel is not loaded from flash + to RAM. Read-write sections, such as the data section and stack, + are still copied to RAM. The XIP kernel is not compressed since + it has to run directly from flash, so it will take more space to + store it. The flash address used to link the kernel object files, + and for storing it, is configuration dependent. Therefore, if you + say Y here, you must know the proper physical address where to + store the kernel image depending on your own flash memory usage. + + Also note that the make target becomes "make xipImage" rather than + "make zImage" or "make Image". The final kernel binary to put in + ROM memory will be arch/riscv/boot/xipImage. + + If unsure, say N. + +config XIP_PHYS_ADDR + hex "XIP Kernel Physical Location" + depends on XIP_KERNEL + default "0x2100" + help + This is the physical address in your flash memory the kernel will + be linked for and stored to. This address is dependent on your + own flash usage. + +config XIP_PHYS_RAM_BASE + hex "Platform Physical RAM address" + depends on XIP_KERNEL + default "0x8000" + help + This is the physical address of RAM in the system. It has to be + explicitly specified to run early relocations of read-write data + from flash to RAM. + endmenu config BUILTIN_DTB - def_bool n + bool depends on OF + default y if XIP_KERNEL menu "Power management options" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 1368d943f1f3..8fcbec03974d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -82,7 +82,11 @@ CHECKFLAGS += -D__riscv -D__riscv_xlen=$(BITS) # Default target when executing plain make boot := arch/riscv/boot +ifeq ($(CONFIG_XIP_KERNEL),y) +KBUILD_IMAGE := $(boot)/xipImage +else KBUILD_IMAGE := $(boot)/Image.gz +endif head-y := arch/riscv/kernel/head.o @@ -95,12 +99,14 @@ PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@ +if
