Re: [PATCH v4 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
On Mon, 2021-03-01 at 11:56 +0100, Robert Foss wrote: > On Mon, 1 Mar 2021 at 10:07, Liu Ying wrote: > > Hi Robert, > > > > On Fri, 2021-02-26 at 14:07 +0100, Robert Foss wrote: > > > Hey Liu, > > > > > > With the below nit straightened out, feel free to add my r-b. > > > > > > Reviewed-by: Robert Foss > > > > Thanks for reviewing this patch. > > > > > On Thu, 18 Feb 2021 at 04:58, Liu Ying wrote: > > > > This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner. > > > > The pixel combiner takes two output streams from a single display > > > > controller and manipulates the two streams to support a number > > > > of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured > > > > as either one screen, two screens, or virtual screens. The pixel > > > > combiner is also responsible for generating some of the control signals > > > > for the pixel link output channel. For now, the driver only supports > > > > the bypass mode. > > > > > > > > Signed-off-by: Liu Ying > > > > --- > > > > v3->v4: > > > > * No change. > > > > > > > > v2->v3: > > > > * No change. > > > > > > > > v1->v2: > > > > * No change. > > > > > > > > drivers/gpu/drm/bridge/Kconfig | 2 + > > > > drivers/gpu/drm/bridge/Makefile| 1 + > > > > drivers/gpu/drm/bridge/imx/Kconfig | 8 + > > > > drivers/gpu/drm/bridge/imx/Makefile| 1 + > > > > .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 > > > > + > > > > 5 files changed, 464 insertions(+) > > > > create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig > > > > create mode 100644 drivers/gpu/drm/bridge/imx/Makefile > > > > create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > > > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig > > > > b/drivers/gpu/drm/bridge/Kconfig > > > > index e4110d6c..84944e0 100644 > > > > --- a/drivers/gpu/drm/bridge/Kconfig > > > > +++ b/drivers/gpu/drm/bridge/Kconfig > > > > @@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig" > > > > > > > > source "drivers/gpu/drm/bridge/cadence/Kconfig" > > > > > > > > +source "drivers/gpu/drm/bridge/imx/Kconfig" > > > > + > > > > source "drivers/gpu/drm/bridge/synopsys/Kconfig" > > > > > > > > endmenu > > > > diff --git a/drivers/gpu/drm/bridge/Makefile > > > > b/drivers/gpu/drm/bridge/Makefile > > > > index 86e7acc..bc80cae 100644 > > > > --- a/drivers/gpu/drm/bridge/Makefile > > > > +++ b/drivers/gpu/drm/bridge/Makefile > > > > @@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o > > > > > > > > obj-y += analogix/ > > > > obj-y += cadence/ > > > > +obj-y += imx/ > > > > obj-y += synopsys/ > > > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig > > > > b/drivers/gpu/drm/bridge/imx/Kconfig > > > > new file mode 100644 > > > > index ..f1c91b6 > > > > --- /dev/null > > > > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > > > > @@ -0,0 +1,8 @@ > > > > +config DRM_IMX8QXP_PIXEL_COMBINER > > > > + tristate "Freescale i.MX8QM/QXP pixel combiner" > > > > + depends on OF > > > > + depends on COMMON_CLK > > > > + select DRM_KMS_HELPER > > > > + help > > > > + Choose this to enable pixel combiner found in > > > > + Freescale i.MX8qm/qxp processors. > > > > diff --git a/drivers/gpu/drm/bridge/imx/Makefile > > > > b/drivers/gpu/drm/bridge/imx/Makefile > > > > new file mode 100644 > > > > index ..7d7c8d6 > > > > --- /dev/null > > > > +++ b/drivers/gpu/drm/bridge/imx/Makefile > > > > @@ -0,0 +1 @@ > > > > +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > > > > diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > > b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > > new file mode 100644 > > > > index ..cd5b1be > > > > --- /dev/null > > > > +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > > @@ -0,0 +1,452 @@ > > > > +// SPDX-License-Identifier: GPL-2.0+ > > > > + > > > > +/* > > > > + * Copyright 2020 NXP > > > > + */ > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#define PC_CTRL_REG0x0 > > > > +#define PC_COMBINE_ENABLE BIT(0) > > > > +#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) > > > > +#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) > > > > +#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) > > > > +#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) > > > > +#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) > > > > +#define PC_DISP_DVALID_POLARITY(n)BIT(4 + 11 * (n)) > > > > +#define PC_DISP_DVALID_POLARITY_POS(n)DISP_DVALID_POLARITY(n) > > > > +#define PC_VSYNC_MASK_ENABLE BIT(5) > > > > +#define
Re: [PATCH v4 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
On Mon, 1 Mar 2021 at 10:07, Liu Ying wrote: > > Hi Robert, > > On Fri, 2021-02-26 at 14:07 +0100, Robert Foss wrote: > > Hey Liu, > > > > With the below nit straightened out, feel free to add my r-b. > > > > Reviewed-by: Robert Foss > > Thanks for reviewing this patch. > > > > > On Thu, 18 Feb 2021 at 04:58, Liu Ying wrote: > > > This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner. > > > The pixel combiner takes two output streams from a single display > > > controller and manipulates the two streams to support a number > > > of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured > > > as either one screen, two screens, or virtual screens. The pixel > > > combiner is also responsible for generating some of the control signals > > > for the pixel link output channel. For now, the driver only supports > > > the bypass mode. > > > > > > Signed-off-by: Liu Ying > > > --- > > > v3->v4: > > > * No change. > > > > > > v2->v3: > > > * No change. > > > > > > v1->v2: > > > * No change. > > > > > > drivers/gpu/drm/bridge/Kconfig | 2 + > > > drivers/gpu/drm/bridge/Makefile| 1 + > > > drivers/gpu/drm/bridge/imx/Kconfig | 8 + > > > drivers/gpu/drm/bridge/imx/Makefile| 1 + > > > .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 > > > + > > > 5 files changed, 464 insertions(+) > > > create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig > > > create mode 100644 drivers/gpu/drm/bridge/imx/Makefile > > > create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig > > > b/drivers/gpu/drm/bridge/Kconfig > > > index e4110d6c..84944e0 100644 > > > --- a/drivers/gpu/drm/bridge/Kconfig > > > +++ b/drivers/gpu/drm/bridge/Kconfig > > > @@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig" > > > > > > source "drivers/gpu/drm/bridge/cadence/Kconfig" > > > > > > +source "drivers/gpu/drm/bridge/imx/Kconfig" > > > + > > > source "drivers/gpu/drm/bridge/synopsys/Kconfig" > > > > > > endmenu > > > diff --git a/drivers/gpu/drm/bridge/Makefile > > > b/drivers/gpu/drm/bridge/Makefile > > > index 86e7acc..bc80cae 100644 > > > --- a/drivers/gpu/drm/bridge/Makefile > > > +++ b/drivers/gpu/drm/bridge/Makefile > > > @@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o > > > > > > obj-y += analogix/ > > > obj-y += cadence/ > > > +obj-y += imx/ > > > obj-y += synopsys/ > > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig > > > b/drivers/gpu/drm/bridge/imx/Kconfig > > > new file mode 100644 > > > index ..f1c91b6 > > > --- /dev/null > > > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > > > @@ -0,0 +1,8 @@ > > > +config DRM_IMX8QXP_PIXEL_COMBINER > > > + tristate "Freescale i.MX8QM/QXP pixel combiner" > > > + depends on OF > > > + depends on COMMON_CLK > > > + select DRM_KMS_HELPER > > > + help > > > + Choose this to enable pixel combiner found in > > > + Freescale i.MX8qm/qxp processors. > > > diff --git a/drivers/gpu/drm/bridge/imx/Makefile > > > b/drivers/gpu/drm/bridge/imx/Makefile > > > new file mode 100644 > > > index ..7d7c8d6 > > > --- /dev/null > > > +++ b/drivers/gpu/drm/bridge/imx/Makefile > > > @@ -0,0 +1 @@ > > > +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > > > diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > new file mode 100644 > > > index ..cd5b1be > > > --- /dev/null > > > +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > @@ -0,0 +1,452 @@ > > > +// SPDX-License-Identifier: GPL-2.0+ > > > + > > > +/* > > > + * Copyright 2020 NXP > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > +#include > > > + > > > +#define PC_CTRL_REG0x0 > > > +#define PC_COMBINE_ENABLE BIT(0) > > > +#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) > > > +#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) > > > +#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) > > > +#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) > > > +#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) > > > +#define PC_DISP_DVALID_POLARITY(n)BIT(4 + 11 * (n)) > > > +#define PC_DISP_DVALID_POLARITY_POS(n)DISP_DVALID_POLARITY(n) > > > +#define PC_VSYNC_MASK_ENABLE BIT(5) > > > +#define PC_SKIP_MODE BIT(6) > > > +#define PC_SKIP_NUMBER_MASK GENMASK(12, 7) > > > +#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, > > > (n)) > > > +#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16) > > > +#define PC_DISP0_PIX_DATA_FORMAT(fmt) \ > > > +
Re: [PATCH v4 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
Hi Robert, On Fri, 2021-02-26 at 14:07 +0100, Robert Foss wrote: > Hey Liu, > > With the below nit straightened out, feel free to add my r-b. > > Reviewed-by: Robert Foss Thanks for reviewing this patch. > > On Thu, 18 Feb 2021 at 04:58, Liu Ying wrote: > > This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner. > > The pixel combiner takes two output streams from a single display > > controller and manipulates the two streams to support a number > > of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured > > as either one screen, two screens, or virtual screens. The pixel > > combiner is also responsible for generating some of the control signals > > for the pixel link output channel. For now, the driver only supports > > the bypass mode. > > > > Signed-off-by: Liu Ying > > --- > > v3->v4: > > * No change. > > > > v2->v3: > > * No change. > > > > v1->v2: > > * No change. > > > > drivers/gpu/drm/bridge/Kconfig | 2 + > > drivers/gpu/drm/bridge/Makefile| 1 + > > drivers/gpu/drm/bridge/imx/Kconfig | 8 + > > drivers/gpu/drm/bridge/imx/Makefile| 1 + > > .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 > > + > > 5 files changed, 464 insertions(+) > > create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig > > create mode 100644 drivers/gpu/drm/bridge/imx/Makefile > > create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > > index e4110d6c..84944e0 100644 > > --- a/drivers/gpu/drm/bridge/Kconfig > > +++ b/drivers/gpu/drm/bridge/Kconfig > > @@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig" > > > > source "drivers/gpu/drm/bridge/cadence/Kconfig" > > > > +source "drivers/gpu/drm/bridge/imx/Kconfig" > > + > > source "drivers/gpu/drm/bridge/synopsys/Kconfig" > > > > endmenu > > diff --git a/drivers/gpu/drm/bridge/Makefile > > b/drivers/gpu/drm/bridge/Makefile > > index 86e7acc..bc80cae 100644 > > --- a/drivers/gpu/drm/bridge/Makefile > > +++ b/drivers/gpu/drm/bridge/Makefile > > @@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o > > > > obj-y += analogix/ > > obj-y += cadence/ > > +obj-y += imx/ > > obj-y += synopsys/ > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig > > b/drivers/gpu/drm/bridge/imx/Kconfig > > new file mode 100644 > > index ..f1c91b6 > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > > @@ -0,0 +1,8 @@ > > +config DRM_IMX8QXP_PIXEL_COMBINER > > + tristate "Freescale i.MX8QM/QXP pixel combiner" > > + depends on OF > > + depends on COMMON_CLK > > + select DRM_KMS_HELPER > > + help > > + Choose this to enable pixel combiner found in > > + Freescale i.MX8qm/qxp processors. > > diff --git a/drivers/gpu/drm/bridge/imx/Makefile > > b/drivers/gpu/drm/bridge/imx/Makefile > > new file mode 100644 > > index ..7d7c8d6 > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/imx/Makefile > > @@ -0,0 +1 @@ > > +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > > diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > new file mode 100644 > > index ..cd5b1be > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > @@ -0,0 +1,452 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > + > > +#define PC_CTRL_REG0x0 > > +#define PC_COMBINE_ENABLE BIT(0) > > +#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) > > +#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) > > +#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) > > +#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) > > +#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) > > +#define PC_DISP_DVALID_POLARITY(n)BIT(4 + 11 * (n)) > > +#define PC_DISP_DVALID_POLARITY_POS(n)DISP_DVALID_POLARITY(n) > > +#define PC_VSYNC_MASK_ENABLE BIT(5) > > +#define PC_SKIP_MODE BIT(6) > > +#define PC_SKIP_NUMBER_MASK GENMASK(12, 7) > > +#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n)) > > +#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16) > > +#define PC_DISP0_PIX_DATA_FORMAT(fmt) \ > > + FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, > > (fmt)) > > +#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19) > > +#define PC_DISP1_PIX_DATA_FORMAT(fmt) \ > > + FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, > > (fmt)) > > + > > +#define PC_BUF_PARA_REG
Re: [PATCH v4 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
Hey Liu, With the below nit straightened out, feel free to add my r-b. Reviewed-by: Robert Foss On Thu, 18 Feb 2021 at 04:58, Liu Ying wrote: > > This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner. > The pixel combiner takes two output streams from a single display > controller and manipulates the two streams to support a number > of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured > as either one screen, two screens, or virtual screens. The pixel > combiner is also responsible for generating some of the control signals > for the pixel link output channel. For now, the driver only supports > the bypass mode. > > Signed-off-by: Liu Ying > --- > v3->v4: > * No change. > > v2->v3: > * No change. > > v1->v2: > * No change. > > drivers/gpu/drm/bridge/Kconfig | 2 + > drivers/gpu/drm/bridge/Makefile| 1 + > drivers/gpu/drm/bridge/imx/Kconfig | 8 + > drivers/gpu/drm/bridge/imx/Makefile| 1 + > .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 > + > 5 files changed, 464 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig > create mode 100644 drivers/gpu/drm/bridge/imx/Makefile > create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > index e4110d6c..84944e0 100644 > --- a/drivers/gpu/drm/bridge/Kconfig > +++ b/drivers/gpu/drm/bridge/Kconfig > @@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig" > > source "drivers/gpu/drm/bridge/cadence/Kconfig" > > +source "drivers/gpu/drm/bridge/imx/Kconfig" > + > source "drivers/gpu/drm/bridge/synopsys/Kconfig" > > endmenu > diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile > index 86e7acc..bc80cae 100644 > --- a/drivers/gpu/drm/bridge/Makefile > +++ b/drivers/gpu/drm/bridge/Makefile > @@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o > > obj-y += analogix/ > obj-y += cadence/ > +obj-y += imx/ > obj-y += synopsys/ > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig > b/drivers/gpu/drm/bridge/imx/Kconfig > new file mode 100644 > index ..f1c91b6 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > @@ -0,0 +1,8 @@ > +config DRM_IMX8QXP_PIXEL_COMBINER > + tristate "Freescale i.MX8QM/QXP pixel combiner" > + depends on OF > + depends on COMMON_CLK > + select DRM_KMS_HELPER > + help > + Choose this to enable pixel combiner found in > + Freescale i.MX8qm/qxp processors. > diff --git a/drivers/gpu/drm/bridge/imx/Makefile > b/drivers/gpu/drm/bridge/imx/Makefile > new file mode 100644 > index ..7d7c8d6 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > new file mode 100644 > index ..cd5b1be > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c > @@ -0,0 +1,452 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright 2020 NXP > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#define PC_CTRL_REG0x0 > +#define PC_COMBINE_ENABLE BIT(0) > +#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) > +#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) > +#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) > +#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) > +#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) > +#define PC_DISP_DVALID_POLARITY(n)BIT(4 + 11 * (n)) > +#define PC_DISP_DVALID_POLARITY_POS(n)DISP_DVALID_POLARITY(n) > +#define PC_VSYNC_MASK_ENABLE BIT(5) > +#define PC_SKIP_MODE BIT(6) > +#define PC_SKIP_NUMBER_MASK GENMASK(12, 7) > +#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n)) > +#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16) > +#define PC_DISP0_PIX_DATA_FORMAT(fmt) \ > + FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, > (fmt)) > +#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19) > +#define PC_DISP1_PIX_DATA_FORMAT(fmt) \ > + FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, > (fmt)) > + > +#define PC_BUF_PARA_REG0x10 This register is unused, keeping it in here to avoid future headaches seems like a good idea. > +#define PC_BUF_ACTIVE_DEPTH_MASK GENMASK(10, 0) > +#define PC_BUF_ACTIVE_DEPTH(n) > FIELD_PREP(PC_BUF_ACTIVE_DEPTH_MASK, (n)) > + > +#define PC_SW_RESET_REG0x20 > +#define PC_SW_RESET_N BIT(0) > +#define
[PATCH v4 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two screens, or virtual screens. The pixel
combiner is also responsible for generating some of the control signals
for the pixel link output channel. For now, the driver only supports
the bypass mode.
Signed-off-by: Liu Ying
---
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile| 1 +
drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile| 1 +
.../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 +
5 files changed, 464 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6c..84944e0 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig"
source "drivers/gpu/drm/bridge/cadence/Kconfig"
+source "drivers/gpu/drm/bridge/imx/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc..bc80cae 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
obj-y += cadence/
+obj-y += imx/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig
b/drivers/gpu/drm/bridge/imx/Kconfig
new file mode 100644
index ..f1c91b6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -0,0 +1,8 @@
+config DRM_IMX8QXP_PIXEL_COMBINER
+ tristate "Freescale i.MX8QM/QXP pixel combiner"
+ depends on OF
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable pixel combiner found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile
b/drivers/gpu/drm/bridge/imx/Makefile
new file mode 100644
index ..7d7c8d6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
new file mode 100644
index ..cd5b1be
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define PC_CTRL_REG0x0
+#define PC_COMBINE_ENABLE BIT(0)
+#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n))
+#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n))
+#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n)
+#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n))
+#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n)
+#define PC_DISP_DVALID_POLARITY(n)BIT(4 + 11 * (n))
+#define PC_DISP_DVALID_POLARITY_POS(n)DISP_DVALID_POLARITY(n)
+#define PC_VSYNC_MASK_ENABLE BIT(5)
+#define PC_SKIP_MODE BIT(6)
+#define PC_SKIP_NUMBER_MASK GENMASK(12, 7)
+#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n))
+#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16)
+#define PC_DISP0_PIX_DATA_FORMAT(fmt) \
+ FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt))
+#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19)
+#define PC_DISP1_PIX_DATA_FORMAT(fmt) \
+ FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt))
+
+#define PC_BUF_PARA_REG0x10
+#define PC_BUF_ACTIVE_DEPTH_MASK GENMASK(10, 0)
+#define PC_BUF_ACTIVE_DEPTH(n)
FIELD_PREP(PC_BUF_ACTIVE_DEPTH_MASK, (n))
+
+#define PC_SW_RESET_REG0x20
+#define PC_SW_RESET_N BIT(0)
+#define PC_DISP_SW_RESET_N(n) BIT(1 + (n))
+#define PC_FULL_RESET_N (PC_SW_RESET_N |\
+PC_DISP_SW_RESET_N(0) |\
+PC_DISP_SW_RESET_N(1))
+
+#define PC_REG_SET 0x4
+#define PC_REG_CLR 0x8
+
+#define DRIVER_NAME"imx8qxp-pixel-combiner"
+
+enum imx8qxp_pc_pix_data_format {
+ RGB,
+ YUV444,
+ YUV422,
+
