Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Tue, Aug 25, 2015 at 12:16 PM, punnaiah choudary kalluri
wrote:
> Hi Rob,
>
> On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring wrote:
>> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
>> wrote:
>>> Device-tree binding documentation for Xilinx zynqmp dma engine used in
>>> Zynq UltraScale+ MPSoC.
>>>
>>> Signed-off-by: Punnaiah Choudary Kalluri
>>> ---
>>> Changes in v4:
>>> - None
>>> Changes in v3:
>>> - None
>>> Changes in v2:
>>> - None
>>> ---
>>> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
>>>
>>> 1 files changed, 61 insertions(+), 0 deletions(-)
>>> create mode 100644
>>> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>> new file mode 100644
>>> index 000..e4f92b9
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>> @@ -0,0 +1,61 @@
>>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
>>> +memory to device and device to memory transfers. It also has flow
>>> +control and rate control support for slave/peripheral dma access.
>>> +
>>> +Required properties:
>>> +- compatible: Should be "xlnx,zynqmp-dma-1.0"
>>> +- #dma-cells: Should be <1>, a single cell holding a line request number
>>> +- reg: Memory map for module access
>>> +- interrupt-parent: Interrupt controller the interrupt is routed through
>>> +- interrupts: Should contain DMA channel interrupt
>>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
>>> +
>>> +Optional properties:
>>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter
>>> + gather dma mode
>>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
>>> +source AXI transaction
>>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the
>>> data
>>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side
>>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for
>>> the
>>> + descriptor read are marked Non-coherent
>>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
>>> + source descriptor payload are marked Non-coherent
>>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
>>> + dst descriptor payload are marked Non-coherent
>>
>> Do you really need 3? dma-coherent property doesn't work for you?
>>
>> Not that it should dictate the binding, but the kernel doesn't support
>> a device needing both coherent and non-coherent DMA ops.
>
> I will get back to you shortly on this
Yes. dma-coherent property works. I will modify the bindings.
Thanks,
Punnaiah
>
>>
>>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
>>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read
>>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
>>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
>>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read
>>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write
>>
>> These signals are generally part of the coherent or not setting. This
>> allows for potentially invalid combinations.
>>
>> Plus you have a copy/paste error.
>
> I will fix this.
>
> Thanks,
> Punnaiah
>>
>>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2
>>> values
>>> + i.e 1,2,4,8 and 16
>>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
>>> values
>>> + i.e 1,2,4,8 and 16
>>> +
>>> +Example:
>>> +
>>> +fpd_dma_chan1: dma@FD50 {
>>> + compatible = "xlnx,zynqmp-dma-1.0";
>>> + reg = <0x0 0xFD50 0x1000>;
>>> + #dma_cells = <1>;
>>> + interrupt-parent = <>;
>>> + interrupts = <0 117 4>;
>>> + xlnx,bus-width = <128>;
>>> + xlnx,include-sg;
>>> + xlnx,overfetch;
>>> + xlnx,ratectrl = <0>;
>>> + xlnx,src-issue = <16>;
>>> + xlnx,desc-axi-cohrnt;
>>> + xlnx,src-axi-cohrnt;
>>> + xlnx,dst-axi-cohrnt;
>>> + xlnx,desc-axi-qos = <0>;
>>> + xlnx,desc-axi-cache = <0>;
>>> + xlnx,src-axi-qos = <0>;
>>> + xlnx,src-axi-cache = <2>;
>>> + xlnx,dst-axi-qos = <0>;
>>> + xlnx,dst-axi-cache = <2>;
>>> + xlnx,src-burst-len = <4>;
>>> + xlnx,dst-burst-len = <4>;
>>> +};
>>> --
>>> 1.7.4
>>>
>>>
>>> ___
>>> linux-arm-kernel mailing list
>>> linux-arm-ker...@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Tue, Aug 25, 2015 at 12:16 PM, punnaiah choudary kalluri
punn...@xilinx.com wrote:
Hi Rob,
On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring robherri...@gmail.com wrote:
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..e4f92b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,61 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible: Should be xlnx,zynqmp-dma-1.0
+- #dma-cells: Should be 1, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the
data
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for
the
+ descriptor read are marked Non-coherent
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
Do you really need 3? dma-coherent property doesn't work for you?
Not that it should dictate the binding, but the kernel doesn't support
a device needing both coherent and non-coherent DMA ops.
I will get back to you shortly on this
Yes. dma-coherent property works. I will modify the bindings.
Thanks,
Punnaiah
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
These signals are generally part of the coherent or not setting. This
allows for potentially invalid combinations.
Plus you have a copy/paste error.
I will fix this.
Thanks,
Punnaiah
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = xlnx,zynqmp-dma-1.0;
+ reg = 0x0 0xFD50 0x1000;
+ #dma_cells = 1;
+ interrupt-parent = gic;
+ interrupts = 0 117 4;
+ xlnx,bus-width = 128;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = 0;
+ xlnx,src-issue = 16;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = 0;
+ xlnx,desc-axi-cache = 0;
+ xlnx,src-axi-qos = 0;
+ xlnx,src-axi-cache = 2;
+ xlnx,dst-axi-qos = 0;
+ xlnx,dst-axi-cache = 2;
+ xlnx,src-burst-len = 4;
+ xlnx,dst-burst-len = 4;
+};
--
1.7.4
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Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Hi Rob,
On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring wrote:
> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
> wrote:
>> Device-tree binding documentation for Xilinx zynqmp dma engine used in
>> Zynq UltraScale+ MPSoC.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri
>> ---
>> Changes in v4:
>> - None
>> Changes in v3:
>> - None
>> Changes in v2:
>> - None
>> ---
>> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
>>
>> 1 files changed, 61 insertions(+), 0 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> new file mode 100644
>> index 000..e4f92b9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> @@ -0,0 +1,61 @@
>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
>> +memory to device and device to memory transfers. It also has flow
>> +control and rate control support for slave/peripheral dma access.
>> +
>> +Required properties:
>> +- compatible: Should be "xlnx,zynqmp-dma-1.0"
>> +- #dma-cells: Should be <1>, a single cell holding a line request number
>> +- reg: Memory map for module access
>> +- interrupt-parent: Interrupt controller the interrupt is routed through
>> +- interrupts: Should contain DMA channel interrupt
>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
>> +
>> +Optional properties:
>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter
>> + gather dma mode
>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
>> +source AXI transaction
>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the
>> data
>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side
>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
>> + descriptor read are marked Non-coherent
>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
>> + source descriptor payload are marked Non-coherent
>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
>> + dst descriptor payload are marked Non-coherent
>
> Do you really need 3? dma-coherent property doesn't work for you?
>
> Not that it should dictate the binding, but the kernel doesn't support
> a device needing both coherent and non-coherent DMA ops.
I will get back to you shortly on this
>
>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read
>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write
>
> These signals are generally part of the coherent or not setting. This
> allows for potentially invalid combinations.
>
> Plus you have a copy/paste error.
I will fix this.
Thanks,
Punnaiah
>
>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2
>> values
>> + i.e 1,2,4,8 and 16
>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
>> values
>> + i.e 1,2,4,8 and 16
>> +
>> +Example:
>> +
>> +fpd_dma_chan1: dma@FD50 {
>> + compatible = "xlnx,zynqmp-dma-1.0";
>> + reg = <0x0 0xFD50 0x1000>;
>> + #dma_cells = <1>;
>> + interrupt-parent = <>;
>> + interrupts = <0 117 4>;
>> + xlnx,bus-width = <128>;
>> + xlnx,include-sg;
>> + xlnx,overfetch;
>> + xlnx,ratectrl = <0>;
>> + xlnx,src-issue = <16>;
>> + xlnx,desc-axi-cohrnt;
>> + xlnx,src-axi-cohrnt;
>> + xlnx,dst-axi-cohrnt;
>> + xlnx,desc-axi-qos = <0>;
>> + xlnx,desc-axi-cache = <0>;
>> + xlnx,src-axi-qos = <0>;
>> + xlnx,src-axi-cache = <2>;
>> + xlnx,dst-axi-qos = <0>;
>> + xlnx,dst-axi-cache = <2>;
>> + xlnx,src-burst-len = <4>;
>> + xlnx,dst-burst-len = <4>;
>> +};
>> --
>> 1.7.4
>>
>>
>> ___
>> linux-arm-kernel mailing list
>> linux-arm-ker...@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Hi Rob,
On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring robherri...@gmail.com wrote:
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..e4f92b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,61 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible: Should be xlnx,zynqmp-dma-1.0
+- #dma-cells: Should be 1, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the
data
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+ descriptor read are marked Non-coherent
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
Do you really need 3? dma-coherent property doesn't work for you?
Not that it should dictate the binding, but the kernel doesn't support
a device needing both coherent and non-coherent DMA ops.
I will get back to you shortly on this
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
These signals are generally part of the coherent or not setting. This
allows for potentially invalid combinations.
Plus you have a copy/paste error.
I will fix this.
Thanks,
Punnaiah
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = xlnx,zynqmp-dma-1.0;
+ reg = 0x0 0xFD50 0x1000;
+ #dma_cells = 1;
+ interrupt-parent = gic;
+ interrupts = 0 117 4;
+ xlnx,bus-width = 128;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = 0;
+ xlnx,src-issue = 16;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = 0;
+ xlnx,desc-axi-cache = 0;
+ xlnx,src-axi-qos = 0;
+ xlnx,src-axi-cache = 2;
+ xlnx,dst-axi-qos = 0;
+ xlnx,dst-axi-cache = 2;
+ xlnx,src-burst-len = 4;
+ xlnx,dst-burst-len = 4;
+};
--
1.7.4
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Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine used in
> Zynq UltraScale+ MPSoC.
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
> Changes in v4:
> - None
> Changes in v3:
> - None
> Changes in v2:
> - None
> ---
> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
>
> 1 files changed, 61 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> new file mode 100644
> index 000..e4f92b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> @@ -0,0 +1,61 @@
> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
> +memory to device and device to memory transfers. It also has flow
> +control and rate control support for slave/peripheral dma access.
> +
> +Required properties:
> +- compatible: Should be "xlnx,zynqmp-dma-1.0"
> +- #dma-cells: Should be <1>, a single cell holding a line request number
> +- reg: Memory map for module access
> +- interrupt-parent: Interrupt controller the interrupt is routed through
> +- interrupts: Should contain DMA channel interrupt
> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
> +
> +Optional properties:
> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter
> + gather dma mode
> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
> +source AXI transaction
> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
> +- xlnx,src-issue: Number of AXI outstanding transactions on source side
> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
> + descriptor read are marked Non-coherent
> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
> + source descriptor payload are marked Non-coherent
> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
> + dst descriptor payload are marked Non-coherent
Do you really need 3? dma-coherent property doesn't work for you?
Not that it should dictate the binding, but the kernel doesn't support
a device needing both coherent and non-coherent DMA ops.
> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read
> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read
> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write
These signals are generally part of the coherent or not setting. This
allows for potentially invalid combinations.
Plus you have a copy/paste error.
> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2
> values
> + i.e 1,2,4,8 and 16
> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
> values
> + i.e 1,2,4,8 and 16
> +
> +Example:
> +
> +fpd_dma_chan1: dma@FD50 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x0 0xFD50 0x1000>;
> + #dma_cells = <1>;
> + interrupt-parent = <>;
> + interrupts = <0 117 4>;
> + xlnx,bus-width = <128>;
> + xlnx,include-sg;
> + xlnx,overfetch;
> + xlnx,ratectrl = <0>;
> + xlnx,src-issue = <16>;
> + xlnx,desc-axi-cohrnt;
> + xlnx,src-axi-cohrnt;
> + xlnx,dst-axi-cohrnt;
> + xlnx,desc-axi-qos = <0>;
> + xlnx,desc-axi-cache = <0>;
> + xlnx,src-axi-qos = <0>;
> + xlnx,src-axi-cache = <2>;
> + xlnx,dst-axi-qos = <0>;
> + xlnx,dst-axi-cache = <2>;
> + xlnx,src-burst-len = <4>;
> + xlnx,dst-burst-len = <4>;
> +};
> --
> 1.7.4
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
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Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Mon, Aug 24, 2015 at 7:17 PM, Lars-Peter Clausen wrote: > On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote: > [...] >> +Optional properties: >> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter >> +gather dma mode >> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for >> + source AXI transaction >> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the >> data >> +- xlnx,src-issue: Number of AXI outstanding transactions on source side >> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the >> + descriptor read are marked Non-coherent >> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the >> + source descriptor payload are marked Non-coherent >> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the >> + dst descriptor payload are marked Non-coherent >> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch >> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read >> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write >> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. >> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read >> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write >> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 >> values >> + i.e 1,2,4,8 and 16 >> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 >> values >> + i.e 1,2,4,8 and 16 > > None of these really belong into the devicetree. This is all runtime > configuration data. This is a general purpose dma and provides more flexibility to the user for configuring the descriptor, data and bus parameters. one way is as you said these parameters can be configured at runtime but i didn't find a way configuring the channel at runtime for mem to mem transfers. I have checked the device_config function description and it is strictly meant for slave operations only. So, i didn't see anything wrong having these parameter values from the device tree as these all are hw parameters. Regards, Punnaiah > > - Lars -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote: [...] > +Optional properties: > +- xlnx,include-sg: Indicates the controller to operate in simple or scatter > +gather dma mode > +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for > + source AXI transaction > +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data > +- xlnx,src-issue: Number of AXI outstanding transactions on source side > +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the > + descriptor read are marked Non-coherent > +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the > + source descriptor payload are marked Non-coherent > +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the > + dst descriptor payload are marked Non-coherent > +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch > +- xlnx,src-axi-qos: AXI QOS bits to be used for data read > +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write > +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. > +- xlnx,desc-axi-cache: AXI cache bits to be used for data read > +- xlnx,desc-axi-cache: AXI cache bits to be used for data write > +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 > values > + i.e 1,2,4,8 and 16 > +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 > values > + i.e 1,2,4,8 and 16 None of these really belong into the devicetree. This is all runtime configuration data. - Lars -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote: [...] +Optional properties: +- xlnx,include-sg: Indicates the controller to operate in simple or scatter +gather dma mode +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for + source AXI transaction +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data +- xlnx,src-issue: Number of AXI outstanding transactions on source side +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the + descriptor read are marked Non-coherent +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the + source descriptor payload are marked Non-coherent +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the + dst descriptor payload are marked Non-coherent +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch +- xlnx,src-axi-qos: AXI QOS bits to be used for data read +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. +- xlnx,desc-axi-cache: AXI cache bits to be used for data read +- xlnx,desc-axi-cache: AXI cache bits to be used for data write +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values + i.e 1,2,4,8 and 16 +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values + i.e 1,2,4,8 and 16 None of these really belong into the devicetree. This is all runtime configuration data. - Lars -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Mon, Aug 24, 2015 at 7:17 PM, Lars-Peter Clausen l...@metafoo.de wrote: On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote: [...] +Optional properties: +- xlnx,include-sg: Indicates the controller to operate in simple or scatter +gather dma mode +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for + source AXI transaction +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data +- xlnx,src-issue: Number of AXI outstanding transactions on source side +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the + descriptor read are marked Non-coherent +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the + source descriptor payload are marked Non-coherent +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the + dst descriptor payload are marked Non-coherent +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch +- xlnx,src-axi-qos: AXI QOS bits to be used for data read +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. +- xlnx,desc-axi-cache: AXI cache bits to be used for data read +- xlnx,desc-axi-cache: AXI cache bits to be used for data write +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values + i.e 1,2,4,8 and 16 +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values + i.e 1,2,4,8 and 16 None of these really belong into the devicetree. This is all runtime configuration data. This is a general purpose dma and provides more flexibility to the user for configuring the descriptor, data and bus parameters. one way is as you said these parameters can be configured at runtime but i didn't find a way configuring the channel at runtime for mem to mem transfers. I have checked the device_config function description and it is strictly meant for slave operations only. So, i didn't see anything wrong having these parameter values from the device tree as these all are hw parameters. Regards, Punnaiah - Lars -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..e4f92b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,61 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible: Should be xlnx,zynqmp-dma-1.0
+- #dma-cells: Should be 1, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+ descriptor read are marked Non-coherent
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
Do you really need 3? dma-coherent property doesn't work for you?
Not that it should dictate the binding, but the kernel doesn't support
a device needing both coherent and non-coherent DMA ops.
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
These signals are generally part of the coherent or not setting. This
allows for potentially invalid combinations.
Plus you have a copy/paste error.
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = xlnx,zynqmp-dma-1.0;
+ reg = 0x0 0xFD50 0x1000;
+ #dma_cells = 1;
+ interrupt-parent = gic;
+ interrupts = 0 117 4;
+ xlnx,bus-width = 128;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = 0;
+ xlnx,src-issue = 16;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = 0;
+ xlnx,desc-axi-cache = 0;
+ xlnx,src-axi-qos = 0;
+ xlnx,src-axi-cache = 2;
+ xlnx,dst-axi-qos = 0;
+ xlnx,dst-axi-cache = 2;
+ xlnx,src-burst-len = 4;
+ xlnx,dst-burst-len = 4;
+};
--
1.7.4
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Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Hi Moritz,
Thanks. I will take care of these suggestions in next version
Regards,
Punnaiah
On Fri, Aug 21, 2015 at 10:12 PM, Moritz Fischer
wrote:
> Hi all,
>
> sorry for HTML mail spam last night ... couple of nits below
>
> On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah Choudary Kalluri
> wrote:
>> Device-tree binding documentation for Xilinx zynqmp dma engine used in
>> Zynq UltraScale+ MPSoC.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri
>> ---
>> Changes in v4:
>> - None
>> Changes in v3:
>> - None
>> Changes in v2:
>> - None
>> ---
>> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
>>
>> 1 files changed, 61 insertions(+), 0 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> new file mode 100644
>> index 000..e4f92b9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> @@ -0,0 +1,61 @@
>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
>> +memory to device and device to memory transfers. It also has flow
>> +control and rate control support for slave/peripheral dma access.
>
> How about: The Xilinx ZynqMP DMA engine does support memory to memory
> transfers,
> memory to device and device to memory transfers. It also has flow
> control and rate control
> support for slave / peripheral DMA access.
>> +
>> +Required properties:
>> +- compatible: Should be "xlnx,zynqmp-dma-1.0"
>> +- #dma-cells: Should be <1>, a single cell holding a line request number
>> +- reg: Memory map for module access
>> +- interrupt-parent: Interrupt controller the interrupt is routed through
>> +- interrupts: Should contain DMA channel interrupt
>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
>> +
>> +Optional properties:
>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter
>> + gather dma mode
> s/dma/DMA
>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
>> +source AXI transaction
>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the
>> data
> (Maybe) s/Tells/Determines/
>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side
>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
>> + descriptor read are marked Non-coherent
> (Maybe) s/Tells/Determines/
>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
>> + source descriptor payload are marked Non-coherent
> same
>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
>> + dst descriptor payload are marked Non-coherent
>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read
>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write
>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2
>> values
>> + i.e 1,2,4,8 and 16
>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
>> values
>> + i.e 1,2,4,8 and 16
>> +
>> +Example:
>> +
>> +fpd_dma_chan1: dma@FD50 {
>> + compatible = "xlnx,zynqmp-dma-1.0";
>> + reg = <0x0 0xFD50 0x1000>;
>> + #dma_cells = <1>;
> #dma-cells = <1>;
>> + interrupt-parent = <>;
>> + interrupts = <0 117 4>;
>> + xlnx,bus-width = <128>;
>> + xlnx,include-sg;
>> + xlnx,overfetch;
>> + xlnx,ratectrl = <0>;
>> + xlnx,src-issue = <16>;
>> + xlnx,desc-axi-cohrnt;
>> + xlnx,src-axi-cohrnt;
>> + xlnx,dst-axi-cohrnt;
>> + xlnx,desc-axi-qos = <0>;
>> + xlnx,desc-axi-cache = <0>;
>> + xlnx,src-axi-qos = <0>;
>> + xlnx,src-axi-cache = <2>;
>> + xlnx,dst-axi-qos = <0>;
>> + xlnx,dst-axi-cache = <2>;
>> + xlnx,src-burst-len = <4>;
>> + xlnx,dst-burst-len = <4>;
>> +};
>> --
>> 1.7.4
>>
>>
>> ___
>> linux-arm-kernel mailing list
>> linux-arm-ker...@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> Cheers,
>
> Moritz
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Hi Moritz,
Thanks. I will take care of these suggestions in next version
Regards,
Punnaiah
On Fri, Aug 21, 2015 at 10:12 PM, Moritz Fischer
moritz.fisc...@ettus.com wrote:
Hi all,
sorry for HTML mail spam last night ... couple of nits below
On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..e4f92b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,61 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
How about: The Xilinx ZynqMP DMA engine does support memory to memory
transfers,
memory to device and device to memory transfers. It also has flow
control and rate control
support for slave / peripheral DMA access.
+
+Required properties:
+- compatible: Should be xlnx,zynqmp-dma-1.0
+- #dma-cells: Should be 1, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
s/dma/DMA
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the
data
(Maybe) s/Tells/Determines/
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+ descriptor read are marked Non-coherent
(Maybe) s/Tells/Determines/
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
same
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = xlnx,zynqmp-dma-1.0;
+ reg = 0x0 0xFD50 0x1000;
+ #dma_cells = 1;
#dma-cells = 1;
+ interrupt-parent = gic;
+ interrupts = 0 117 4;
+ xlnx,bus-width = 128;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = 0;
+ xlnx,src-issue = 16;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = 0;
+ xlnx,desc-axi-cache = 0;
+ xlnx,src-axi-qos = 0;
+ xlnx,src-axi-cache = 2;
+ xlnx,dst-axi-qos = 0;
+ xlnx,dst-axi-cache = 2;
+ xlnx,src-burst-len = 4;
+ xlnx,dst-burst-len = 4;
+};
--
1.7.4
___
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Cheers,
Moritz
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Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Hi all,
sorry for HTML mail spam last night ... couple of nits below
On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah Choudary Kalluri
wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine used in
> Zynq UltraScale+ MPSoC.
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
> Changes in v4:
> - None
> Changes in v3:
> - None
> Changes in v2:
> - None
> ---
> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
>
> 1 files changed, 61 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> new file mode 100644
> index 000..e4f92b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> @@ -0,0 +1,61 @@
> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
> +memory to device and device to memory transfers. It also has flow
> +control and rate control support for slave/peripheral dma access.
How about: The Xilinx ZynqMP DMA engine does support memory to memory transfers,
memory to device and device to memory transfers. It also has flow
control and rate control
support for slave / peripheral DMA access.
> +
> +Required properties:
> +- compatible: Should be "xlnx,zynqmp-dma-1.0"
> +- #dma-cells: Should be <1>, a single cell holding a line request number
> +- reg: Memory map for module access
> +- interrupt-parent: Interrupt controller the interrupt is routed through
> +- interrupts: Should contain DMA channel interrupt
> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
> +
> +Optional properties:
> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter
> + gather dma mode
s/dma/DMA
> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
> +source AXI transaction
> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
(Maybe) s/Tells/Determines/
> +- xlnx,src-issue: Number of AXI outstanding transactions on source side
> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
> + descriptor read are marked Non-coherent
(Maybe) s/Tells/Determines/
> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
> + source descriptor payload are marked Non-coherent
same
> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
> + dst descriptor payload are marked Non-coherent
> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read
> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read
> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write
> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2
> values
> + i.e 1,2,4,8 and 16
> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
> values
> + i.e 1,2,4,8 and 16
> +
> +Example:
> +
> +fpd_dma_chan1: dma@FD50 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x0 0xFD50 0x1000>;
> + #dma_cells = <1>;
#dma-cells = <1>;
> + interrupt-parent = <>;
> + interrupts = <0 117 4>;
> + xlnx,bus-width = <128>;
> + xlnx,include-sg;
> + xlnx,overfetch;
> + xlnx,ratectrl = <0>;
> + xlnx,src-issue = <16>;
> + xlnx,desc-axi-cohrnt;
> + xlnx,src-axi-cohrnt;
> + xlnx,dst-axi-cohrnt;
> + xlnx,desc-axi-qos = <0>;
> + xlnx,desc-axi-cache = <0>;
> + xlnx,src-axi-qos = <0>;
> + xlnx,src-axi-cache = <2>;
> + xlnx,dst-axi-qos = <0>;
> + xlnx,dst-axi-cache = <2>;
> + xlnx,src-burst-len = <4>;
> + xlnx,dst-burst-len = <4>;
> +};
> --
> 1.7.4
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Cheers,
Moritz
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Hi all,
sorry for HTML mail spam last night ... couple of nits below
On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..e4f92b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,61 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
How about: The Xilinx ZynqMP DMA engine does support memory to memory transfers,
memory to device and device to memory transfers. It also has flow
control and rate control
support for slave / peripheral DMA access.
+
+Required properties:
+- compatible: Should be xlnx,zynqmp-dma-1.0
+- #dma-cells: Should be 1, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
s/dma/DMA
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
(Maybe) s/Tells/Determines/
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+ descriptor read are marked Non-coherent
(Maybe) s/Tells/Determines/
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
same
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2
values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = xlnx,zynqmp-dma-1.0;
+ reg = 0x0 0xFD50 0x1000;
+ #dma_cells = 1;
#dma-cells = 1;
+ interrupt-parent = gic;
+ interrupts = 0 117 4;
+ xlnx,bus-width = 128;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = 0;
+ xlnx,src-issue = 16;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = 0;
+ xlnx,desc-axi-cache = 0;
+ xlnx,src-axi-qos = 0;
+ xlnx,src-axi-cache = 2;
+ xlnx,dst-axi-qos = 0;
+ xlnx,dst-axi-cache = 2;
+ xlnx,src-burst-len = 4;
+ xlnx,dst-burst-len = 4;
+};
--
1.7.4
___
linux-arm-kernel mailing list
linux-arm-ker...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Cheers,
Moritz
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On 08/20/2015 08:18 AM, Vinod Koul wrote: > On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote: +- interrupts: Should contain DMA channel interrupt >>> channel interrupt or interrupts, former says it is plural >> >> ZynqMP DMA has single interrupt for each channel So, that is the reason >> i have explicitly mentioned it as interrupt ( not interrupts). >> >> Please let me know if you still want it to be plural. > > The example had multiple values so plural sounds right > I expect you are talking about this "interrupts = <0 117 4>;" It is 3 cells format used on ARM based on gic spec which is on SPI interrupt 117 active high level-sensitive Documentation/devicetree/bindings/arm/gic.txt Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote: > >> +- interrupts: Should contain DMA channel interrupt > > channel interrupt or interrupts, former says it is plural > > ZynqMP DMA has single interrupt for each channel So, that is the reason > i have explicitly mentioned it as interrupt ( not interrupts). > > Please let me know if you still want it to be plural. The example had multiple values so plural sounds right -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Thu, Aug 20, 2015 at 11:22 AM, Vinod Koul wrote: > On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote: >> Device-tree binding documentation for Xilinx zynqmp dma engine used in >> Zynq UltraScale+ MPSoC. >> >> Signed-off-by: Punnaiah Choudary Kalluri >> --- >> Changes in v4: >> - None >> Changes in v3: >> - None >> Changes in v2: >> - None >> --- >> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 >> >> 1 files changed, 61 insertions(+), 0 deletions(-) >> create mode 100644 >> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >> >> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >> new file mode 100644 >> index 000..e4f92b9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >> @@ -0,0 +1,61 @@ >> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, >> +memory to device and device to memory transfers. It also has flow >> +control and rate control support for slave/peripheral dma access. >> + >> +Required properties: >> +- compatible: Should be "xlnx,zynqmp-dma-1.0" >> +- #dma-cells: Should be <1>, a single cell holding a line request number >> +- reg: Memory map for module access >> +- interrupt-parent: Interrupt controller the interrupt is routed through >> +- interrupts: Should contain DMA channel interrupt > channel interrupt or interrupts, former says it is plural ZynqMP DMA has single interrupt for each channel So, that is the reason i have explicitly mentioned it as interrupt ( not interrupts). Please let me know if you still want it to be plural. Regards, Punnaiah > > -- > ~Vinod > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On 08/20/2015 08:18 AM, Vinod Koul wrote: On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote: +- interrupts: Should contain DMA channel interrupt channel interrupt or interrupts, former says it is plural ZynqMP DMA has single interrupt for each channel So, that is the reason i have explicitly mentioned it as interrupt ( not interrupts). Please let me know if you still want it to be plural. The example had multiple values so plural sounds right I expect you are talking about this interrupts = 0 117 4; It is 3 cells format used on ARM based on gic spec which is on SPI interrupt 117 active high level-sensitive Documentation/devicetree/bindings/arm/gic.txt Thanks, Michal -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Thu, Aug 20, 2015 at 11:22 AM, Vinod Koul vinod.k...@intel.com wrote: On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote: Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com --- Changes in v4: - None Changes in v3: - None Changes in v2: - None --- .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 1 files changed, 61 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 000..e4f92b9 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,61 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible: Should be xlnx,zynqmp-dma-1.0 +- #dma-cells: Should be 1, a single cell holding a line request number +- reg: Memory map for module access +- interrupt-parent: Interrupt controller the interrupt is routed through +- interrupts: Should contain DMA channel interrupt channel interrupt or interrupts, former says it is plural ZynqMP DMA has single interrupt for each channel So, that is the reason i have explicitly mentioned it as interrupt ( not interrupts). Please let me know if you still want it to be plural. Regards, Punnaiah -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote: +- interrupts: Should contain DMA channel interrupt channel interrupt or interrupts, former says it is plural ZynqMP DMA has single interrupt for each channel So, that is the reason i have explicitly mentioned it as interrupt ( not interrupts). Please let me know if you still want it to be plural. The example had multiple values so plural sounds right -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote: > Device-tree binding documentation for Xilinx zynqmp dma engine used in > Zynq UltraScale+ MPSoC. > > Signed-off-by: Punnaiah Choudary Kalluri > --- > Changes in v4: > - None > Changes in v3: > - None > Changes in v2: > - None > --- > .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 > > 1 files changed, 61 insertions(+), 0 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > new file mode 100644 > index 000..e4f92b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > @@ -0,0 +1,61 @@ > +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, > +memory to device and device to memory transfers. It also has flow > +control and rate control support for slave/peripheral dma access. > + > +Required properties: > +- compatible: Should be "xlnx,zynqmp-dma-1.0" > +- #dma-cells: Should be <1>, a single cell holding a line request number > +- reg: Memory map for module access > +- interrupt-parent: Interrupt controller the interrupt is routed through > +- interrupts: Should contain DMA channel interrupt channel interrupt or interrupts, former says it is plural -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote: Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com --- Changes in v4: - None Changes in v3: - None Changes in v2: - None --- .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 1 files changed, 61 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 000..e4f92b9 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,61 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible: Should be xlnx,zynqmp-dma-1.0 +- #dma-cells: Should be 1, a single cell holding a line request number +- reg: Memory map for module access +- interrupt-parent: Interrupt controller the interrupt is routed through +- interrupts: Should contain DMA channel interrupt channel interrupt or interrupts, former says it is plural -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..e4f92b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,61 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible: Should be "xlnx,zynqmp-dma-1.0"
+- #dma-cells: Should be <1>, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+ descriptor read are marked Non-coherent
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xFD50 0x1000>;
+ #dma_cells = <1>;
+ interrupt-parent = <>;
+ interrupts = <0 117 4>;
+ xlnx,bus-width = <128>;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = <0>;
+ xlnx,src-issue = <16>;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = <0>;
+ xlnx,desc-axi-cache = <0>;
+ xlnx,src-axi-qos = <0>;
+ xlnx,src-axi-cache = <2>;
+ xlnx,dst-axi-qos = <0>;
+ xlnx,dst-axi-cache = <2>;
+ xlnx,src-burst-len = <4>;
+ xlnx,dst-burst-len = <4>;
+};
--
1.7.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
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b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
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+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible: Should be xlnx,zynqmp-dma-1.0
+- #dma-cells: Should be 1, a single cell holding a line request number
+- reg: Memory map for module access
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt
+- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+ gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+ descriptor read are marked Non-coherent
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+ source descriptor payload are marked Non-coherent
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+ dst descriptor payload are marked Non-coherent
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values
+ i.e 1,2,4,8 and 16
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values
+ i.e 1,2,4,8 and 16
+
+Example:
+
+fpd_dma_chan1: dma@FD50 {
+ compatible = xlnx,zynqmp-dma-1.0;
+ reg = 0x0 0xFD50 0x1000;
+ #dma_cells = 1;
+ interrupt-parent = gic;
+ interrupts = 0 117 4;
+ xlnx,bus-width = 128;
+ xlnx,include-sg;
+ xlnx,overfetch;
+ xlnx,ratectrl = 0;
+ xlnx,src-issue = 16;
+ xlnx,desc-axi-cohrnt;
+ xlnx,src-axi-cohrnt;
+ xlnx,dst-axi-cohrnt;
+ xlnx,desc-axi-qos = 0;
+ xlnx,desc-axi-cache = 0;
+ xlnx,src-axi-qos = 0;
+ xlnx,src-axi-cache = 2;
+ xlnx,dst-axi-qos = 0;
+ xlnx,dst-axi-cache = 2;
+ xlnx,src-burst-len = 4;
+ xlnx,dst-burst-len = 4;
+};
--
1.7.4
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