Re: [PATCH v4 1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support
Hi Long, Thank you for the patch! Yet something to improve: [auto build test ERROR on linus/master] [also build test ERROR on v4.20-rc6 next-20181207] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Long-Cheng/add-uart-DMA-function/20181210-125624 config: s390-allmodconfig (attached as .config) compiler: s390x-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=s390 All error/warnings (new ones prefixed by >>): >> drivers/dma/mediatek/8250_mtk_dma.c:29:30: error: >> 'CONFIG_SERIAL_8250_NR_UARTS' undeclared here (not in a function); did you >> mean 'CONFIG_SERIAL_RP2_NR_UARTS'? #define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2) ^ >> drivers/dma/mediatek/8250_mtk_dma.c:75:25: note: in expansion of macro >> 'MTK_APDMA_CHANNELS' void __iomem *mem_base[MTK_APDMA_CHANNELS]; ^~ vim +29 drivers/dma/mediatek/8250_mtk_dma.c 27 28 #define MTK_APDMA_DEFAULT_REQUESTS 127 > 29 #define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2) 30 31 #define VFF_EN_BBIT(0) 32 #define VFF_STOP_B BIT(0) 33 #define VFF_FLUSH_B BIT(0) 34 #define VFF_4G_SUPPORT_BBIT(0) 35 #define VFF_RX_INT_EN0_BBIT(0) /*rx valid size >= vff thre*/ 36 #define VFF_RX_INT_EN1_BBIT(1) 37 #define VFF_TX_INT_EN_B BIT(0) /*tx left size >= vff thre*/ 38 #define VFF_WARM_RST_B BIT(0) 39 #define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1)) 40 #define VFF_TX_INT_FLAG_CLR_B 0 41 #define VFF_STOP_CLR_B 0 42 #define VFF_FLUSH_CLR_B 0 43 #define VFF_INT_EN_CLR_B0 44 #define VFF_4G_SUPPORT_CLR_B0 45 46 /* interrupt trigger level for tx */ 47 #define VFF_TX_THRE(n) ((n) * 7 / 8) 48 /* interrupt trigger level for rx */ 49 #define VFF_RX_THRE(n) ((n) * 3 / 4) 50 51 #define MTK_DMA_RING_SIZE 0xU 52 /* invert this bit when wrap ring head again*/ 53 #define MTK_DMA_RING_WRAP 0x1U 54 55 #define VFF_INT_FLAG0x00 56 #define VFF_INT_EN 0x04 57 #define VFF_EN 0x08 58 #define VFF_RST 0x0c 59 #define VFF_STOP0x10 60 #define VFF_FLUSH 0x14 61 #define VFF_ADDR0x1c 62 #define VFF_LEN 0x24 63 #define VFF_THRE0x28 64 #define VFF_WPT 0x2c 65 #define VFF_RPT 0x30 66 /*TX: the buffer size HW can read. RX: the buffer size SW can read.*/ 67 #define VFF_VALID_SIZE 0x3c 68 /*TX: the buffer size SW can write. RX: the buffer size HW can write.*/ 69 #define VFF_LEFT_SIZE 0x40 70 #define VFF_DEBUG_STATUS0x50 71 #define VFF_4G_SUPPORT 0x54 72 73 struct mtk_dmadev { 74 struct dma_device ddev; > 75 void __iomem *mem_base[MTK_APDMA_CHANNELS]; 76 spinlock_t lock; /* dma dev lock */ 77 struct tasklet_struct task; 78 struct list_head pending; 79 struct clk *clk; 80 unsigned int dma_requests; 81 bool support_33bits; 82 unsigned int dma_irq[MTK_APDMA_CHANNELS]; 83 struct mtk_chan *ch[MTK_APDMA_CHANNELS]; 84 }; 85 --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip
[resend PATCH v4 1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support
In DMA engine framework, add 8250 mtk dma to support it. Signed-off-by: Long Cheng --- drivers/dma/mediatek/8250_mtk_dma.c | 830 +++ drivers/dma/mediatek/Kconfig| 11 + drivers/dma/mediatek/Makefile |1 + 3 files changed, 842 insertions(+) create mode 100644 drivers/dma/mediatek/8250_mtk_dma.c diff --git a/drivers/dma/mediatek/8250_mtk_dma.c b/drivers/dma/mediatek/8250_mtk_dma.c new file mode 100644 index 000..f79d180 --- /dev/null +++ b/drivers/dma/mediatek/8250_mtk_dma.c @@ -0,0 +1,830 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek 8250 DMA driver. + * + * Copyright (c) 2018 MediaTek Inc. + * Author: Long Cheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" + +#define MTK_APDMA_DEFAULT_REQUESTS 127 +#define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2) + +#define VFF_EN_B BIT(0) +#define VFF_STOP_B BIT(0) +#define VFF_FLUSH_BBIT(0) +#define VFF_4G_SUPPORT_B BIT(0) +#define VFF_RX_INT_EN0_B BIT(0) /*rx valid size >= vff thre*/ +#define VFF_RX_INT_EN1_B BIT(1) +#define VFF_TX_INT_EN_BBIT(0) /*tx left size >= vff thre*/ +#define VFF_WARM_RST_B BIT(0) +#define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1)) +#define VFF_TX_INT_FLAG_CLR_B 0 +#define VFF_STOP_CLR_B 0 +#define VFF_FLUSH_CLR_B0 +#define VFF_INT_EN_CLR_B 0 +#define VFF_4G_SUPPORT_CLR_B 0 + +/* interrupt trigger level for tx */ +#define VFF_TX_THRE(n) ((n) * 7 / 8) +/* interrupt trigger level for rx */ +#define VFF_RX_THRE(n) ((n) * 3 / 4) + +#define MTK_DMA_RING_SIZE 0xU +/* invert this bit when wrap ring head again*/ +#define MTK_DMA_RING_WRAP 0x1U + +#define VFF_INT_FLAG 0x00 +#define VFF_INT_EN 0x04 +#define VFF_EN 0x08 +#define VFF_RST0x0c +#define VFF_STOP 0x10 +#define VFF_FLUSH 0x14 +#define VFF_ADDR 0x1c +#define VFF_LEN0x24 +#define VFF_THRE 0x28 +#define VFF_WPT0x2c +#define VFF_RPT0x30 +/*TX: the buffer size HW can read. RX: the buffer size SW can read.*/ +#define VFF_VALID_SIZE 0x3c +/*TX: the buffer size SW can write. RX: the buffer size HW can write.*/ +#define VFF_LEFT_SIZE 0x40 +#define VFF_DEBUG_STATUS 0x50 +#define VFF_4G_SUPPORT 0x54 + +struct mtk_dmadev { + struct dma_device ddev; + void __iomem *mem_base[MTK_APDMA_CHANNELS]; + spinlock_t lock; /* dma dev lock */ + struct tasklet_struct task; + struct list_head pending; + struct clk *clk; + unsigned int dma_requests; + bool support_33bits; + unsigned int dma_irq[MTK_APDMA_CHANNELS]; + struct mtk_chan *ch[MTK_APDMA_CHANNELS]; +}; + +struct mtk_chan { + struct virt_dma_chan vc; + struct list_head node; + struct dma_slave_config cfg; + void __iomem *base; + struct mtk_dma_desc *desc; + + bool stop; + bool requested; + + unsigned int rx_status; +}; + +struct mtk_dma_sg { + dma_addr_t addr; + unsigned int en;/* number of elements (24-bit) */ + unsigned int fn;/* number of frames (16-bit) */ +}; + +struct mtk_dma_desc { + struct virt_dma_desc vd; + enum dma_transfer_direction dir; + + unsigned int sglen; + struct mtk_dma_sg sg[0]; + + unsigned int len; +}; + +static inline struct mtk_dmadev *to_mtk_dma_dev(struct dma_device *d) +{ + return container_of(d, struct mtk_dmadev, ddev); +} + +static inline struct mtk_chan *to_mtk_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct mtk_chan, vc.chan); +} + +static inline struct mtk_dma_desc *to_mtk_dma_desc + (struct dma_async_tx_descriptor *t) +{ + return container_of(t, struct mtk_dma_desc, vd.tx); +} + +static void mtk_dma_chan_write(struct mtk_chan *c, + unsigned int reg, unsigned int val) +{ + writel(val, c->base + reg); +} + +static unsigned int mtk_dma_chan_read(struct mtk_chan *c, unsigned int reg) +{ + return readl(c->base + reg); +} + +static void mtk_dma_desc_free(struct virt_dma_desc *vd) +{ + struct dma_chan *chan = vd->tx.chan; + struct mtk_chan *c = to_mtk_dma_chan(chan); + + kfree(c->desc); + c->desc = NULL; +} + +static void mtk_dma_tx_flush(struct dma_chan *chan) +{ + struct mtk_chan *c = to_mtk_dma_chan(chan); + + if (mtk_dma_chan_read(c, VFF_FLUSH) == 0U) + mtk_dma_chan_write(c, VFF_FLUSH, VFF_FLUSH_B); +} + +static void mtk_dma_tx_write(struct dma_chan *chan) +{ + struct mtk_chan *c = to_mtk
[PATCH v4 1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support
In DMA engine framework, add 8250 mtk dma to support it. Signed-off-by: Long Cheng --- drivers/dma/mediatek/8250_mtk_dma.c | 830 +++ drivers/dma/mediatek/Kconfig| 11 + drivers/dma/mediatek/Makefile |1 + 3 files changed, 842 insertions(+) create mode 100644 drivers/dma/mediatek/8250_mtk_dma.c diff --git a/drivers/dma/mediatek/8250_mtk_dma.c b/drivers/dma/mediatek/8250_mtk_dma.c new file mode 100644 index 000..f79d180 --- /dev/null +++ b/drivers/dma/mediatek/8250_mtk_dma.c @@ -0,0 +1,830 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek 8250 DMA driver. + * + * Copyright (c) 2018 MediaTek Inc. + * Author: Long Cheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../virt-dma.h" + +#define MTK_APDMA_DEFAULT_REQUESTS 127 +#define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2) + +#define VFF_EN_B BIT(0) +#define VFF_STOP_B BIT(0) +#define VFF_FLUSH_BBIT(0) +#define VFF_4G_SUPPORT_B BIT(0) +#define VFF_RX_INT_EN0_B BIT(0) /*rx valid size >= vff thre*/ +#define VFF_RX_INT_EN1_B BIT(1) +#define VFF_TX_INT_EN_BBIT(0) /*tx left size >= vff thre*/ +#define VFF_WARM_RST_B BIT(0) +#define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1)) +#define VFF_TX_INT_FLAG_CLR_B 0 +#define VFF_STOP_CLR_B 0 +#define VFF_FLUSH_CLR_B0 +#define VFF_INT_EN_CLR_B 0 +#define VFF_4G_SUPPORT_CLR_B 0 + +/* interrupt trigger level for tx */ +#define VFF_TX_THRE(n) ((n) * 7 / 8) +/* interrupt trigger level for rx */ +#define VFF_RX_THRE(n) ((n) * 3 / 4) + +#define MTK_DMA_RING_SIZE 0xU +/* invert this bit when wrap ring head again*/ +#define MTK_DMA_RING_WRAP 0x1U + +#define VFF_INT_FLAG 0x00 +#define VFF_INT_EN 0x04 +#define VFF_EN 0x08 +#define VFF_RST0x0c +#define VFF_STOP 0x10 +#define VFF_FLUSH 0x14 +#define VFF_ADDR 0x1c +#define VFF_LEN0x24 +#define VFF_THRE 0x28 +#define VFF_WPT0x2c +#define VFF_RPT0x30 +/*TX: the buffer size HW can read. RX: the buffer size SW can read.*/ +#define VFF_VALID_SIZE 0x3c +/*TX: the buffer size SW can write. RX: the buffer size HW can write.*/ +#define VFF_LEFT_SIZE 0x40 +#define VFF_DEBUG_STATUS 0x50 +#define VFF_4G_SUPPORT 0x54 + +struct mtk_dmadev { + struct dma_device ddev; + void __iomem *mem_base[MTK_APDMA_CHANNELS]; + spinlock_t lock; /* dma dev lock */ + struct tasklet_struct task; + struct list_head pending; + struct clk *clk; + unsigned int dma_requests; + bool support_33bits; + unsigned int dma_irq[MTK_APDMA_CHANNELS]; + struct mtk_chan *ch[MTK_APDMA_CHANNELS]; +}; + +struct mtk_chan { + struct virt_dma_chan vc; + struct list_head node; + struct dma_slave_config cfg; + void __iomem *base; + struct mtk_dma_desc *desc; + + bool stop; + bool requested; + + unsigned int rx_status; +}; + +struct mtk_dma_sg { + dma_addr_t addr; + unsigned int en;/* number of elements (24-bit) */ + unsigned int fn;/* number of frames (16-bit) */ +}; + +struct mtk_dma_desc { + struct virt_dma_desc vd; + enum dma_transfer_direction dir; + + unsigned int sglen; + struct mtk_dma_sg sg[0]; + + unsigned int len; +}; + +static inline struct mtk_dmadev *to_mtk_dma_dev(struct dma_device *d) +{ + return container_of(d, struct mtk_dmadev, ddev); +} + +static inline struct mtk_chan *to_mtk_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct mtk_chan, vc.chan); +} + +static inline struct mtk_dma_desc *to_mtk_dma_desc + (struct dma_async_tx_descriptor *t) +{ + return container_of(t, struct mtk_dma_desc, vd.tx); +} + +static void mtk_dma_chan_write(struct mtk_chan *c, + unsigned int reg, unsigned int val) +{ + writel(val, c->base + reg); +} + +static unsigned int mtk_dma_chan_read(struct mtk_chan *c, unsigned int reg) +{ + return readl(c->base + reg); +} + +static void mtk_dma_desc_free(struct virt_dma_desc *vd) +{ + struct dma_chan *chan = vd->tx.chan; + struct mtk_chan *c = to_mtk_dma_chan(chan); + + kfree(c->desc); + c->desc = NULL; +} + +static void mtk_dma_tx_flush(struct dma_chan *chan) +{ + struct mtk_chan *c = to_mtk_dma_chan(chan); + + if (mtk_dma_chan_read(c, VFF_FLUSH) == 0U) + mtk_dma_chan_write(c, VFF_FLUSH, VFF_FLUSH_B); +} + +static void mtk_dma_tx_write(struct dma_chan *chan) +{ + struct mtk_chan *c = to_mtk