Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../bindings/clock/qcom,dispcc-sm8x50.yaml| 93 +++
.../dt-bindings/clock/qcom,dispcc-sm8150.h| 1 +
.../dt-bindings/clock/qcom,dispcc-sm8250.h| 66 +
3 files changed, 160 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
create mode 12 include/dt-bindings/clock/qcom,dispcc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
new file mode 100644
index ..0cdf53f41f84
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+
+maintainers:
+ - Jonathan Marek
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on SM8150 and SM8250.
+
+ See also:
+dt-bindings/clock/qcom,dispcc-sm8150.h
+dt-bindings/clock/qcom,dispcc-sm8250.h
+
+properties:
+ compatible:
+enum:
+ - qcom,sm8150-dispcc
+ - qcom,sm8250-dispcc
+
+ clocks:
+items:
+ - description: Board XO source
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+items:
+ - const: bi_tcxo
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dsi1_phy_pll_out_byteclk
+ - const: dsi1_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+
+ '#clock-cells':
+const: 1
+
+ '#reset-cells':
+const: 1
+
+ '#power-domain-cells':
+const: 1
+
+ reg:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+clock-controller@af0 {
+ compatible = "qcom,sm8250-dispcc";
+ reg = <0x0af0 0x1>;
+ clocks = < RPMH_CXO_CLK>,
+ <_phy 0>,
+ <_phy 1>,
+ <_phy 0>,
+ <_phy 1>,
+ <_phy 0>,
+ <_phy 1>;
+ clock-names = "bi_tcxo",
+"dsi0_phy_pll_out_byteclk",
+"dsi0_phy_pll_out_dsiclk",
+"dsi1_phy_pll_out_byteclk",
+"dsi1_phy_pll_out_dsiclk",
+"dp_phy_pll_link_clk",
+"dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+};
+...
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h
b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
new file mode 12
index ..0312b4544acb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h
b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
new file mode 100644
index ..fdaca6ad5c85
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AHB_CLK_SRC 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK5
+#define DISP_CC_MDSS_BYTE1_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK9
+#define DISP_CC_MDSS_DP_AUX1_CLK 10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
+#define DISP_CC_MDSS_DP_AUX_CLK12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC13
+#define DISP_CC_MDSS_DP_LINK1_CLK 14
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
+#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
+#define
