[PATCH v4 1/3] arm64: dts: apq8096-db820c: enable bluetooth node

2018-03-14 Thread Thierry Escande 
Add a new serial node for the Qualcomm BT controller QCA6174. This
allows automatic probing and hci registration through the serdev
framework instead of relying on the userspace helpers.

Signed-off-by: Thierry Escande 
---

v4: no change
v3: no change

v2:
- Fix author email

 arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi  | 14 ++
 .../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi| 17 
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi   | 32 ++
 arch/arm64/boot/dts/qcom/msm8996.dtsi  | 10 +++
 4 files changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
index 24552f19b3fa..172165d84669 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
@@ -36,4 +36,18 @@
drive-strength = <2>;   /* 2 MA */
};
};
+
+   blsp1_uart1_default: blsp1_uart1_default {
+   function = "blsp_uart2";
+   pins = "gpio41", "gpio42", "gpio43", "gpio44";
+   drive-strength = <16>;
+   bias-disable;
+   };
+
+   blsp1_uart1_sleep: blsp1_uart1_sleep {
+   function = "gpio";
+   pins = "gpio41", "gpio42", "gpio43", "gpio44";
+   drive-strength = <2>;
+   bias-disable;
+   };
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index 59b29ddfb6e9..f8d2a3b10b1f 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -26,6 +26,23 @@
};
};
 
+   divclk4_pin_a: divclk4 {
+   pins = "gpio18";
+   function = "func2";
+
+   bias-disable;
+   power-source = ;
+   };
+
+   bt_en_pin_a: bt-en-active {
+   pins = "gpio19";
+   function = "normal";
+
+   output-low;
+   power-source = ;
+   qcom,drive-strength = ;
+   };
+
usb3_vbus_det_gpio: pm8996_gpio22 {
pinconf {
pins = "gpio22";
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 1c8f1b86472d..b05d6bc0b856 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -23,6 +23,7 @@
aliases {
serial0 = _uart1;
serial1 = _uart2;
+   serial2 = _uart1;
i2c0= _i2c2;
i2c1= _i2c1;
i2c2= _i2c0;
@@ -34,7 +35,38 @@
stdout-path = "serial0:115200n8";
};
 
+   clocks {
+   divclk4: divclk4 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "divclk4";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_pin_a>;
+   };
+   };
+
soc {
+   serial@757 {
+   label = "BT-UART";
+   status = "okay";
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_uart1_default>;
+   pinctrl-1 = <_uart1_sleep>;
+
+   bluetooth {
+   compatible = "qcom,qca6174-bt";
+
+   bt-disable-n-gpios = <_gpios 19 
GPIO_ACTIVE_HIGH>;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_en_pin_a>;
+
+   clocks = <>;
+   };
+   };
+
serial@75b {
label = "LS-UART1";
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0a6f7952bbb1..2d54a86a027f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -408,6 +408,16 @@
#clock-cells = <1>;
};
 
+   blsp1_uart1: serial@757 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x0757 0x1000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
blsp1_spi0: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000

[PATCH v4 1/3] arm64: dts: apq8096-db820c: enable bluetooth node

2018-03-14 Thread Thierry Escande 
Add a new serial node for the Qualcomm BT controller QCA6174. This
allows automatic probing and hci registration through the serdev
framework instead of relying on the userspace helpers.

Signed-off-by: Thierry Escande 
---

v4: no change
v3: no change

v2:
- Fix author email

 arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi  | 14 ++
 .../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi| 17 
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi   | 32 ++
 arch/arm64/boot/dts/qcom/msm8996.dtsi  | 10 +++
 4 files changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
index 24552f19b3fa..172165d84669 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
@@ -36,4 +36,18 @@
drive-strength = <2>;   /* 2 MA */
};
};
+
+   blsp1_uart1_default: blsp1_uart1_default {
+   function = "blsp_uart2";
+   pins = "gpio41", "gpio42", "gpio43", "gpio44";
+   drive-strength = <16>;
+   bias-disable;
+   };
+
+   blsp1_uart1_sleep: blsp1_uart1_sleep {
+   function = "gpio";
+   pins = "gpio41", "gpio42", "gpio43", "gpio44";
+   drive-strength = <2>;
+   bias-disable;
+   };
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index 59b29ddfb6e9..f8d2a3b10b1f 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -26,6 +26,23 @@
};
};
 
+   divclk4_pin_a: divclk4 {
+   pins = "gpio18";
+   function = "func2";
+
+   bias-disable;
+   power-source = ;
+   };
+
+   bt_en_pin_a: bt-en-active {
+   pins = "gpio19";
+   function = "normal";
+
+   output-low;
+   power-source = ;
+   qcom,drive-strength = ;
+   };
+
usb3_vbus_det_gpio: pm8996_gpio22 {
pinconf {
pins = "gpio22";
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 1c8f1b86472d..b05d6bc0b856 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -23,6 +23,7 @@
aliases {
serial0 = _uart1;
serial1 = _uart2;
+   serial2 = _uart1;
i2c0= _i2c2;
i2c1= _i2c1;
i2c2= _i2c0;
@@ -34,7 +35,38 @@
stdout-path = "serial0:115200n8";
};
 
+   clocks {
+   divclk4: divclk4 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "divclk4";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_pin_a>;
+   };
+   };
+
soc {
+   serial@757 {
+   label = "BT-UART";
+   status = "okay";
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_uart1_default>;
+   pinctrl-1 = <_uart1_sleep>;
+
+   bluetooth {
+   compatible = "qcom,qca6174-bt";
+
+   bt-disable-n-gpios = <_gpios 19 
GPIO_ACTIVE_HIGH>;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_en_pin_a>;
+
+   clocks = <>;
+   };
+   };
+
serial@75b {
label = "LS-UART1";
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0a6f7952bbb1..2d54a86a027f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -408,6 +408,16 @@
#clock-cells = <1>;
};
 
+   blsp1_uart1: serial@757 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x0757 0x1000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
blsp1_spi0: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
-- 
2.14.1