Re: [PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Brian Norris]

On Tue, Jan 26, 2016 at 03:23:55PM +0800, Yuan Yao wrote:
> Add R/W functions for big- or little-endian registers:
> The qSPI controller's endian is independent of the CPU core's endian.
> So far, the qSPI have two versions for big-endian and little-endian.
> 
> Signed-off-by: Yuan Yao 
> Acked-by: Han xu 

Pushed patches 1, 2, 3, 5, and 7 to l2-mtd.git. Patch 4 seems unrelated,
and patch 6 should go through arm-soc.

Regards,
Brian

Re: [PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Brian Norris]

On Tue, Jan 26, 2016 at 03:23:55PM +0800, Yuan Yao wrote:
> Add R/W functions for big- or little-endian registers:
> The qSPI controller's endian is independent of the CPU core's endian.
> So far, the qSPI have two versions for big-endian and little-endian.
> 
> Signed-off-by: Yuan Yao 
> Acked-by: Han xu 

Pushed patches 1, 2, 3, 5, and 7 to l2-mtd.git. Patch 4 seems unrelated,
and patch 6 should go through arm-soc.

Regards,
Brian

Re: [PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Han Xu]

On Tue, Jan 26, 2016 at 03:23:55PM +0800, Yuan Yao wrote:
> Add R/W functions for big- or little-endian registers:
> The qSPI controller's endian is independent of the CPU core's endian.
> So far, the qSPI have two versions for big-endian and little-endian.
> 
> Signed-off-by: Yuan Yao 
> Acked-by: Han xu 
> ---
> Changed in v4:
> No changes.
> 
> Changed in v3:
> Update my email to 
> 
> Changed in v2:
> Rebase to the lastest code.
> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 157 
> +++---
>  1 file changed, 97 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
> b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 54640f1..04e8a93 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -275,6 +275,7 @@ struct fsl_qspi {
>   u32 clk_rate;
>   unsigned int chip_base_addr; /* We may support two chips. */
>   bool has_second_chip;
> + bool big_endian;
>   struct mutex lock;
>   struct pm_qos_request pm_qos_req;
>  };
> @@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
> *q)
>  }
>  
>  /*
> + * R/W functions for big- or little-endian registers:
> + * The qSPI controller's endian is independent of the CPU core's endian.
> + * So far, although the CPU core is little-endian but the qSPI have two
> + * versions for big-endian and little-endian.
> + */
> +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
> +{
> + if (q->big_endian)
> + iowrite32be(val, addr);
> + else
> + iowrite32(val, addr);
> +}
> +
> +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
> +{
> + if (q->big_endian)
> + return ioread32be(addr);
> + else
> + return ioread32(addr);
> +}
> +
> +/*
>   * An IC bug makes us to re-arrange the 32-bit data.
>   * The following chips, such as IMX6SLX, have fixed this bug.
>   */
> @@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
> *q, u32 a)
>  
>  static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
>  {
> - writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> - writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
> + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> + qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
>  }
>  
>  static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
>  {
> - writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> - writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
> + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> + qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
>  }
>  
>  static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
> @@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
> *dev_id)
>   u32 reg;
>  
>   /* clear interrupt */
> - reg = readl(q->iobase + QUADSPI_FR);
> - writel(reg, q->iobase + QUADSPI_FR);
> + reg = qspi_readl(q, q->iobase + QUADSPI_FR);
> + qspi_writel(q, reg, q->iobase + QUADSPI_FR);
>  
>   if (reg & QUADSPI_FR_TFF_MASK)
>   complete(>c);
> @@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>  
>   /* Clear all the LUT table */
>   for (i = 0; i < QUADSPI_LUT_NUM; i++)
> - writel(0, base + QUADSPI_LUT_BASE + i * 4);
> + qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
>  
>   /* Quad Read */
>   lut_base = SEQID_QUAD_READ * 4;
> @@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   dummy = 8;
>   }
>  
> - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
>   base + QUADSPI_LUT(lut_base));
> - writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
> + qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
>   base + QUADSPI_LUT(lut_base + 1));
>  
>   /* Write enable */
>   lut_base = SEQID_WREN * 4;
> - writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
> + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
> + base + QUADSPI_LUT(lut_base));
>  
>   /* Page Program */
>   lut_base = SEQID_PP * 4;
> @@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   addrlen = ADDR32BIT;
>   }
>  
> - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
>   base + QUADSPI_LUT(lut_base));
> - writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
> + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
> + base + QUADSPI_LUT(lut_base + 1));
>  
>   /* 

Re: [PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Han Xu]

On Tue, Jan 26, 2016 at 03:23:55PM +0800, Yuan Yao wrote:
> Add R/W functions for big- or little-endian registers:
> The qSPI controller's endian is independent of the CPU core's endian.
> So far, the qSPI have two versions for big-endian and little-endian.
> 
> Signed-off-by: Yuan Yao 
> Acked-by: Han xu 
> ---
> Changed in v4:
> No changes.
> 
> Changed in v3:
> Update my email to 
> 
> Changed in v2:
> Rebase to the lastest code.
> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 157 
> +++---
>  1 file changed, 97 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
> b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 54640f1..04e8a93 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -275,6 +275,7 @@ struct fsl_qspi {
>   u32 clk_rate;
>   unsigned int chip_base_addr; /* We may support two chips. */
>   bool has_second_chip;
> + bool big_endian;
>   struct mutex lock;
>   struct pm_qos_request pm_qos_req;
>  };
> @@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
> *q)
>  }
>  
>  /*
> + * R/W functions for big- or little-endian registers:
> + * The qSPI controller's endian is independent of the CPU core's endian.
> + * So far, although the CPU core is little-endian but the qSPI have two
> + * versions for big-endian and little-endian.
> + */
> +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
> +{
> + if (q->big_endian)
> + iowrite32be(val, addr);
> + else
> + iowrite32(val, addr);
> +}
> +
> +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
> +{
> + if (q->big_endian)
> + return ioread32be(addr);
> + else
> + return ioread32(addr);
> +}
> +
> +/*
>   * An IC bug makes us to re-arrange the 32-bit data.
>   * The following chips, such as IMX6SLX, have fixed this bug.
>   */
> @@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
> *q, u32 a)
>  
>  static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
>  {
> - writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> - writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
> + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> + qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
>  }
>  
>  static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
>  {
> - writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> - writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
> + qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> + qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
>  }
>  
>  static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
> @@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
> *dev_id)
>   u32 reg;
>  
>   /* clear interrupt */
> - reg = readl(q->iobase + QUADSPI_FR);
> - writel(reg, q->iobase + QUADSPI_FR);
> + reg = qspi_readl(q, q->iobase + QUADSPI_FR);
> + qspi_writel(q, reg, q->iobase + QUADSPI_FR);
>  
>   if (reg & QUADSPI_FR_TFF_MASK)
>   complete(>c);
> @@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>  
>   /* Clear all the LUT table */
>   for (i = 0; i < QUADSPI_LUT_NUM; i++)
> - writel(0, base + QUADSPI_LUT_BASE + i * 4);
> + qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
>  
>   /* Quad Read */
>   lut_base = SEQID_QUAD_READ * 4;
> @@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   dummy = 8;
>   }
>  
> - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
>   base + QUADSPI_LUT(lut_base));
> - writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
> + qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
>   base + QUADSPI_LUT(lut_base + 1));
>  
>   /* Write enable */
>   lut_base = SEQID_WREN * 4;
> - writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
> + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
> + base + QUADSPI_LUT(lut_base));
>  
>   /* Page Program */
>   lut_base = SEQID_PP * 4;
> @@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   addrlen = ADDR32BIT;
>   }
>  
> - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
>   base + QUADSPI_LUT(lut_base));
> - writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
> + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
> + base + QUADSPI_LUT(lut_base + 1));
>  
>   /* Read Status */
>   lut_base = SEQID_RDSR * 4;
> - 

[PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v4:
No changes.

Changed in v3:
Update my email to 

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+   LUT1(FSL_READ, PAD1, 0x1),
base + 

[PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v4:
No changes.

Changed in v3:
Update my email to 

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+