[PATCH v4 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250

2015-12-13 Thread Chanwoo Choi 
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/boot/dts/exynos3250.dtsi | 147 ++
 1 file changed, 147 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 262b3b1995fd..5cc98cf13173 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -735,6 +735,153 @@
opp-microvolt = <875000>;
};
};
+
+   bus_leftbus: bus_leftbus {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_GDL>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_rightbus: bus_rightbus {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_GDR>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_lcd0: bus_lcd0 {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_160>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_fsys: bus_fsys {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_200>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_mcuisp: bus_mcuisp {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_400_MCUISP>;
+   clock-names = "bus";
+   operating-points-v2 = <_mcuisp_opp_table>;
+   status = "disabled";
+   };
+
+   bus_isp: bus_isp {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_266>;
+   clock-names = "bus";
+   operating-points-v2 = <_isp_opp_table>;
+   status = "disabled";
+   };
+
+   bus_peril: bus_peril {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_100>;
+   clock-names = "bus";
+   operating-points-v2 = <_peril_opp_table>;
+   status = "disabled";
+   };
+
+   bus_mfc: bus_mfc {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_SCLK_MFC>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_leftbus_opp_table: opp_table2 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5000 {
+   opp-hz = /bits/ 64 <5000>;
+   opp-microvolt = <90>;
+   };
+   opp@8000 {
+   opp-hz = /bits/ 64 <8000>;
+   opp-microvolt = <90>;
+   };
+   opp@1 {
+   opp-hz = /bits/ 64 <1>;
+   opp-microvolt = <100>;
+   };
+   opp@13400 {
+   opp-hz = /bits/ 64 <13400>;
+   opp-microvolt = <100>;
+   };
+   opp@2 {
+   opp-hz = /bits/ 64 <2>;
+   opp-microvolt = <100>;
+   };
+   };
+
+   bus_mcuisp_opp_table: opp_table3 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5000 {
+   opp-hz = /bits/ 64 <5000>;
+   };
+

[PATCH v4 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250

2015-12-13 Thread Chanwoo Choi 
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/boot/dts/exynos3250.dtsi | 147 ++
 1 file changed, 147 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 262b3b1995fd..5cc98cf13173 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -735,6 +735,153 @@
opp-microvolt = <875000>;
};
};
+
+   bus_leftbus: bus_leftbus {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_GDL>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_rightbus: bus_rightbus {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_GDR>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_lcd0: bus_lcd0 {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_160>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_fsys: bus_fsys {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_200>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_mcuisp: bus_mcuisp {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_400_MCUISP>;
+   clock-names = "bus";
+   operating-points-v2 = <_mcuisp_opp_table>;
+   status = "disabled";
+   };
+
+   bus_isp: bus_isp {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_266>;
+   clock-names = "bus";
+   operating-points-v2 = <_isp_opp_table>;
+   status = "disabled";
+   };
+
+   bus_peril: bus_peril {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACLK_100>;
+   clock-names = "bus";
+   operating-points-v2 = <_peril_opp_table>;
+   status = "disabled";
+   };
+
+   bus_mfc: bus_mfc {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_SCLK_MFC>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_leftbus_opp_table: opp_table2 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5000 {
+   opp-hz = /bits/ 64 <5000>;
+   opp-microvolt = <90>;
+   };
+   opp@8000 {
+   opp-hz = /bits/ 64 <8000>;
+   opp-microvolt = <90>;
+   };
+   opp@1 {
+   opp-hz = /bits/ 64 <1>;
+   opp-microvolt = <100>;
+   };
+   opp@13400 {
+   opp-hz = /bits/ 64 <13400>;
+   opp-microvolt = <100>;
+   };
+   opp@2 {
+   opp-hz = /bits/ 64 <2>;
+   opp-microvolt = <100>;
+   };
+   };
+
+   bus_mcuisp_opp_table: opp_table3 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5000 {
+   opp-hz = /bits/ 64 <5000>;
+