Re: [PATCH v4 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
On 01/12/15 08:24, Kapil Hali wrote: > These changes cleans up SMP implementaion for Broadcom's > Kona SoC which are required for handling SMP for iProc > family of SoCs at a single place for BCM NSP and BCM Kona. FWIW, I gave this patch a try on a Capri board, and this still brings-up the two CPUs successfully: MMC read: dev # 0, block # 114688, count 32768 ... 100% (32768/32768 blocks) 32768 blocks read: OK ## Starting application at 0x80008000 ... Uncompressing Linux... done, booting the kernel. [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.4.0-rc1-5-ge49c96ed573e (fainelli@fainelli-desktop) (gcc version 4. 8.5 (Broadcom stbgcc-4.8-1.4) ) #605 SMP Tue Dec 1 17:53:02 PST 2015 [0.00] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: BCM28155 AP board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writealloc [0.00] PERCPU: Embedded 12 pages/cpu @ef7d3000 s18752 r8192 d22208 u49152 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260608 [0.00] Kernel command line: console=ttyS0,115200n8 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1009696K/1048576K available (6384K kernel code, 279K rwdata, 2268K rodata, 4152 K init, 218K bss, 22496K reserved, 16384K cma-reserved, 245760K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xf080 - 0xff80 ( 240 MB) [0.00] lowmem : 0xc000 - 0xf000 ( 768 MB) [0.00] pkmap : 0xbfe0 - 0xc000 ( 2 MB) [0.00] modules : 0xbf00 - 0xbfe0 ( 14 MB) [0.00] .text : 0xc0008000 - 0xc087b694 (8654 kB) [0.00] .init : 0xc087c000 - 0xc0c8a000 (4152 kB) [0.00] .data : 0xc0c8a000 - 0xc0ccfdf8 ( 280 kB) [0.00].bss : 0xc0cd2000 - 0xc0d08bac ( 219 kB) [0.00] Hierarchical RCU implementation. [0.00] Build-time adjustment of leaf fanout to 32. [0.00] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. [0.00] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2 [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] __ccu_wait_bit: slave_ccu/0x0484 bit 18 was never set [0.00] __peri_clk_init: error initializing gate for bsc3 [0.00] Broadcom slave_ccu initialization had errors [0.00] sched_clock: 32 bits at 1kHz, resolution 100ns, wraps every 214748364750ns [0.00] Console: colour dummy device 80x30 [0.006000] Calibrating delay loop... 2383.87 BogoMIPS (lpj=1191936) [0.006000] pid_max: default: 32768 minimum: 301 [0.006000] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.006000] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.006000] CPU: Testing write buffer coherency: ok [0.006000] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.006000] Setting up static identity map for 0x800082c0 - 0x80008318 [0.015000] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 [0.015000] Brought up 2 CPUs [0.015000] SMP: Total of 2 processors activated (7200.76 BogoMIPS). [0.015000] CPU: All CPU(s) started in SVC mode. [0.015000] devtmpfs: initialized [0.016000] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 [0.016000] clocksource: jiffies: mask: 0x max_cycles: 0x, max_idle_ns: 19112604462 75000 ns [0.016000] pinctrl core: initialized pinctrl subsystem [0.017000] NET: Registered protocol family 16 [0.017000] DMA: preallocated 256 KiB pool for atomic coherent allocations [0.023000] cpuidle: using governor ladder [0.025000] cpuidle: using governor menu [0.026000] Kona Secure API initialized [0.026000] BCM-L2C-310 cache controller enabled, 16 ways, 512 kB [0.026000] BCM-L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x1e05 [0.026000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. [0.026000] hw-breakpoint: maximum watchpoint size is 4 bytes. [0.033000] SCSI subsystem initialized [0.033000] usbcore: registered new interface driver usbfs [0.033000] usbcore: registered new interface driver hub [0.033000] usbcore: registered new device driver usb [0.033000] Linux video capture interface: v2.00 [0.033000] pps_core: LinuxPPS API ver. 1 registered [0.033000] pps_core: Software ver. 5.3.6 - Copyright 2005-2
Re: [PATCH v4 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
On 01/12/15 08:24, Kapil Hali wrote: > These changes cleans up SMP implementaion for Broadcom's > Kona SoC which are required for handling SMP for iProc > family of SoCs at a single place for BCM NSP and BCM Kona. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
These changes cleans up SMP implementaion for Broadcom's
Kona SoC which are required for handling SMP for iProc
family of SoCs at a single place for BCM NSP and BCM Kona.
Signed-off-by: Kapil Hali
---
arch/arm/boot/dts/bcm11351.dtsi | 2 +-
arch/arm/boot/dts/bcm21664.dtsi | 2 +-
arch/arm/mach-bcm/kona_smp.c| 82 +++--
3 files changed, 56 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 2ddaa51..3dc7a8c 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -31,7 +31,6 @@
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
cpu0: cpu@0 {
device_type = "cpu";
@@ -42,6 +41,7 @@
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ secondary-boot-reg = <0x3500417c>;
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 2016b72..3f525be 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -31,7 +31,6 @@
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x35004178>;
cpu0: cpu@0 {
device_type = "cpu";
@@ -42,6 +41,7 @@
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ secondary-boot-reg = <0x35004178>;
reg = <1>;
};
};
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c
index 66a0465..15af781 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/kona_smp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
* Copyright 2014 Linaro Limited
*
* This program is free software; you can redistribute it and/or
@@ -30,9 +30,10 @@
/* Name of device node property defining secondary boot register location */
#define OF_SECONDARY_BOOT "secondary-boot-reg"
+#define MPIDR_CPUID_BITMASK0x3
/* I/O address of register used to coordinate secondary core startup */
-static u32 secondary_boot;
+static u32 secondary_boot_addr;
/*
* Enable the Cortex A9 Snoop Control Unit
@@ -78,44 +79,68 @@ static int __init scu_a9_enable(void)
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
- struct device_node *node;
+ struct device_node *cpus_node = NULL;
+ struct device_node *cpu_node = NULL;
int ret;
- BUG_ON(secondary_boot); /* We're called only once */
-
/*
* This function is only called via smp_ops->smp_prepare_cpu().
* That only happens if a "/cpus" device tree node exists
* and has an "enable-method" property that selects the SMP
* operations defined herein.
*/
- node = of_find_node_by_path("/cpus");
- BUG_ON(!node);
-
- /*
-* Our secondary enable method requires a "secondary-boot-reg"
-* property to specify a register address used to request the
-* ROM code boot a secondary code. If we have any trouble
-* getting this we fall back to uniprocessor mode.
-*/
- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
- node->name);
- ret = -ENOENT; /* Arrange to disable SMP */
- goto out;
+ cpus_node = of_find_node_by_path("/cpus");
+ if (!cpus_node)
+ return;
+
+ for_each_child_of_node(cpus_node, cpu_node) {
+ u32 cpuid;
+
+ if (of_node_cmp(cpu_node->type, "cpu"))
+ continue;
+
+ if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
+ pr_debug("%s: missing reg property\n",
+cpu_node->full_name);
+ ret = -ENOENT;
+ goto out;
+ }
+
+ /*
+* "secondary-boot-reg" property should be defined only
+* for secondary cpu
+*/
+ if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
+ /*
+* Our secondary enable method requires a
+* "secondary-boot-reg" property to specify a register
+* address used to request the ROM code boot a secondary
+
