Re: [PATCH v4 3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote:
>
> On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
> > Add driver code for the SiFive FU740 PRCI IP block. This IP block
> > handles reset and clock control for the SiFive FU740 device and
> > implements SoC-level clock tree controls and dividers.
> >
> > This driver contains bug fixes and contributions from
> > Henry Styles
> > Erik Danie
> > Pragnesh Patel
> >
> > Signed-off-by: Zong Li
> > Reviewed-by: Pragnesh Patel
> > Cc: Henry Styles
> > Cc: Erik Danie
> > Cc: Pragnesh Patel
> > ---
> > drivers/clk/sifive/Kconfig| 4 +-
> > drivers/clk/sifive/Makefile | 1 +
> > drivers/clk/sifive/fu740-prci.c | 122 ++
> > drivers/clk/sifive/fu740-prci.h | 21 +++
> > drivers/clk/sifive/sifive-prci.c | 120 +
> > drivers/clk/sifive/sifive-prci.h | 88 +
> > include/dt-bindings/clock/sifive-fu740-prci.h | 23
>
> I don't see the bindings in Documentation, but assuming they're in flight
Yash is working on some DT bindings, but he suggests that I could
integrate PRCI's binding in this patch set, and rename the prci
binding file, so I would add the binding in the next version.
>
> Acked-by: Palmer Dabbelt
>
> Thanks!
>
> > 7 files changed, 377 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/clk/sifive/fu740-prci.c
> > create mode 100644 drivers/clk/sifive/fu740-prci.h
> > create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
> >
> > diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
> > index ab48cf7e0105..1c14eb20c066 100644
> > --- a/drivers/clk/sifive/Kconfig
> > +++ b/drivers/clk/sifive/Kconfig
> > @@ -13,7 +13,7 @@ config CLK_SIFIVE_PRCI
> > select CLK_ANALOGBITS_WRPLL_CLN28HPC
> > help
> > Supports the Power Reset Clock interface (PRCI) IP block found in
> > - FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
> > - enable this driver.
> > + FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
> > + FU740 SoCs, enable this driver.
> >
> > endif
> > diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
> > index fe3e2cb4c4d8..2c05798e4ba4 100644
> > --- a/drivers/clk/sifive/Makefile
> > +++ b/drivers/clk/sifive/Makefile
> > @@ -2,3 +2,4 @@
> > obj-y += sifive-prci.o
> >
> > obj-$(CONFIG_CLK_SIFIVE_PRCI)+= fu540-prci.o
> > +obj-$(CONFIG_CLK_SIFIVE_PRCI)+= fu740-prci.o
> > diff --git a/drivers/clk/sifive/fu740-prci.c
> > b/drivers/clk/sifive/fu740-prci.c
> > new file mode 100644
> > index ..3b87e273c3eb
> > --- /dev/null
> > +++ b/drivers/clk/sifive/fu740-prci.c
> > @@ -0,0 +1,122 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2018-2019 SiFive, Inc.
> > + * Wesley Terpstra
> > + * Paul Walmsley
> > + * Zong Li
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include
> > +#include
> > +#include "sifive-prci.h"
> > +
> > +/* PRCI integration data for each WRPLL instance */
> > +
> > +static struct __prci_wrpll_data __prci_corepll_data = {
> > + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
> > + .enable_bypass = sifive_prci_coreclksel_use_hfclk,
> > + .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_ddrpll_data = {
> > + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_gemgxlpll_data = {
> > + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_dvfscorepll_data = {
> > + .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
> > + .enable_bypass = sifive_prci_corepllsel_use_corepll,
> > + .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_hfpclkpll_data = {
> > + .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
> > + .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
> > + .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_cltxpll_data = {
> > + .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
> > +};
> > +
> > +/* Linux clock framework integration */
> > +
> > +static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
> > + .set_rate = sifive_prci_wrpll_set_rate,
> > + .round_rate = sifive_prci_wrpll_round_rate,
> > + .recalc_rate
Re: [PATCH v4 3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote:
>
> On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
> > Add driver code for the SiFive FU740 PRCI IP block. This IP block
> > handles reset and clock control for the SiFive FU740 device and
> > implements SoC-level clock tree controls and dividers.
> >
> > This driver contains bug fixes and contributions from
> > Henry Styles
> > Erik Danie
> > Pragnesh Patel
>
> Is there a datasheet for this chip? It's geneally best to link to one, in
> case
> someone needs to sort out issues in the future.
>
We have a product brief as follow in public now, I would add the link
of it in the next version patch. Thanks.
https://sifive.cdn.prismic.io/sifive/c05b8ddd-e043-45a6-8a29-2a137090236f_HiFive+Unmatched+Product+Brief+%28released%29.pdf
> >
> > Signed-off-by: Zong Li
> > Reviewed-by: Pragnesh Patel
> > Cc: Henry Styles
> > Cc: Erik Danie
> > Cc: Pragnesh Patel
> > ---
> > drivers/clk/sifive/Kconfig| 4 +-
> > drivers/clk/sifive/Makefile | 1 +
> > drivers/clk/sifive/fu740-prci.c | 122 ++
> > drivers/clk/sifive/fu740-prci.h | 21 +++
> > drivers/clk/sifive/sifive-prci.c | 120 +
> > drivers/clk/sifive/sifive-prci.h | 88 +
> > include/dt-bindings/clock/sifive-fu740-prci.h | 23
> > 7 files changed, 377 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/clk/sifive/fu740-prci.c
> > create mode 100644 drivers/clk/sifive/fu740-prci.h
> > create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
> >
> > diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
> > index ab48cf7e0105..1c14eb20c066 100644
> > --- a/drivers/clk/sifive/Kconfig
> > +++ b/drivers/clk/sifive/Kconfig
> > @@ -13,7 +13,7 @@ config CLK_SIFIVE_PRCI
> > select CLK_ANALOGBITS_WRPLL_CLN28HPC
> > help
> > Supports the Power Reset Clock interface (PRCI) IP block found in
> > - FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
> > - enable this driver.
> > + FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
> > + FU740 SoCs, enable this driver.
> >
> > endif
> > diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
> > index fe3e2cb4c4d8..2c05798e4ba4 100644
> > --- a/drivers/clk/sifive/Makefile
> > +++ b/drivers/clk/sifive/Makefile
> > @@ -2,3 +2,4 @@
> > obj-y += sifive-prci.o
> >
> > obj-$(CONFIG_CLK_SIFIVE_PRCI)+= fu540-prci.o
> > +obj-$(CONFIG_CLK_SIFIVE_PRCI)+= fu740-prci.o
> > diff --git a/drivers/clk/sifive/fu740-prci.c
> > b/drivers/clk/sifive/fu740-prci.c
> > new file mode 100644
> > index ..3b87e273c3eb
> > --- /dev/null
> > +++ b/drivers/clk/sifive/fu740-prci.c
> > @@ -0,0 +1,122 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2018-2019 SiFive, Inc.
> > + * Wesley Terpstra
> > + * Paul Walmsley
> > + * Zong Li
>
> Presumably it's copyright 2020 as well, as that's the current year? Also,
> IIUC
> the copyright lines should be independent from each other. In other words,
> rather than
>
>
>C ... 2020 SiFive
>Zong
>
> this should be
>
>C ... 2020 SiFive
>C ... 2020 Zong
>
> and the rest of this should be dropped in favor of the SPDX.
Ok, many thanks for correcting that, I would modify it in the next
version patch.
>
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include
> > +#include
> > +#include "sifive-prci.h"
> > +
> > +/* PRCI integration data for each WRPLL instance */
> > +
> > +static struct __prci_wrpll_data __prci_corepll_data = {
> > + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
> > + .enable_bypass = sifive_prci_coreclksel_use_hfclk,
> > + .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_ddrpll_data = {
> > + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_gemgxlpll_data = {
> > + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_dvfscorepll_data = {
> > + .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
> > + .enable_bypass = sifive_prci_corepllsel_use_corepll,
> > + .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
> > +};
> > +
> > +static struct __prci_wrpll_data __prci_hfpclkpll_data = {
> > + .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
> > + .enable_bypass =
Re: [PATCH v4 3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Is there a datasheet for this chip? It's geneally best to link to one, in case
someone needs to sort out issues in the future.
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig| 4 +-
drivers/clk/sifive/Makefile | 1 +
drivers/clk/sifive/fu740-prci.c | 122 ++
drivers/clk/sifive/fu740-prci.h | 21 +++
drivers/clk/sifive/sifive-prci.c | 120 +
drivers/clk/sifive/sifive-prci.h | 88 +
include/dt-bindings/clock/sifive-fu740-prci.h | 23
7 files changed, 377 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index ab48cf7e0105..1c14eb20c066 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -13,7 +13,7 @@ config CLK_SIFIVE_PRCI
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in
- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
- enable this driver.
+ FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
+ FU740 SoCs, enable this driver.
endif
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index fe3e2cb4c4d8..2c05798e4ba4 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -2,3 +2,4 @@
obj-y += sifive-prci.o
obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o
+obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu740-prci.o
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
new file mode 100644
index ..3b87e273c3eb
--- /dev/null
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
Presumably it's copyright 2020 as well, as that's the current year? Also, IIUC
the copyright lines should be independent from each other. In other words,
rather than
C ... 2020 SiFive
Zong
this should be
C ... 2020 SiFive
C ... 2020 Zong
and the rest of this should be dropped in favor of the SPDX.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include "sifive-prci.h"
+
+/* PRCI integration data for each WRPLL instance */
+
+static struct __prci_wrpll_data __prci_corepll_data = {
+ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_coreclksel_use_hfclk,
+ .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
+};
+
+static struct __prci_wrpll_data __prci_ddrpll_data = {
+ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_gemgxlpll_data = {
+ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_dvfscorepll_data = {
+ .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_corepllsel_use_corepll,
+ .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
+};
+
+static struct __prci_wrpll_data __prci_hfpclkpll_data = {
+ .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
+ .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
+};
+
+static struct __prci_wrpll_data __prci_cltxpll_data = {
+ .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
+};
+
+/* Linux clock framework integration */
+
+static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
+ .set_rate = sifive_prci_wrpll_set_rate,
+ .round_rate = sifive_prci_wrpll_round_rate,
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
+ .recalc_rate = sifive_prci_tlclksel_recalc_rate,
+};
+
+static const struct clk_ops
Re: [PATCH v4 3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
On Wed, 11 Nov 2020 02:06:07 PST (-0800), zong...@sifive.com wrote:
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig| 4 +-
drivers/clk/sifive/Makefile | 1 +
drivers/clk/sifive/fu740-prci.c | 122 ++
drivers/clk/sifive/fu740-prci.h | 21 +++
drivers/clk/sifive/sifive-prci.c | 120 +
drivers/clk/sifive/sifive-prci.h | 88 +
include/dt-bindings/clock/sifive-fu740-prci.h | 23
I don't see the bindings in Documentation, but assuming they're in flight
Acked-by: Palmer Dabbelt
Thanks!
7 files changed, 377 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index ab48cf7e0105..1c14eb20c066 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -13,7 +13,7 @@ config CLK_SIFIVE_PRCI
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in
- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
- enable this driver.
+ FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
+ FU740 SoCs, enable this driver.
endif
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index fe3e2cb4c4d8..2c05798e4ba4 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -2,3 +2,4 @@
obj-y += sifive-prci.o
obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o
+obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu740-prci.o
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
new file mode 100644
index ..3b87e273c3eb
--- /dev/null
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include "sifive-prci.h"
+
+/* PRCI integration data for each WRPLL instance */
+
+static struct __prci_wrpll_data __prci_corepll_data = {
+ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_coreclksel_use_hfclk,
+ .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
+};
+
+static struct __prci_wrpll_data __prci_ddrpll_data = {
+ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_gemgxlpll_data = {
+ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_dvfscorepll_data = {
+ .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_corepllsel_use_corepll,
+ .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
+};
+
+static struct __prci_wrpll_data __prci_hfpclkpll_data = {
+ .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
+ .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
+};
+
+static struct __prci_wrpll_data __prci_cltxpll_data = {
+ .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
+};
+
+/* Linux clock framework integration */
+
+static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
+ .set_rate = sifive_prci_wrpll_set_rate,
+ .round_rate = sifive_prci_wrpll_round_rate,
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
+ .recalc_rate = sifive_prci_tlclksel_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
+ .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
+};
+
+/* List of clock controls provided by the PRCI */
+struct __prci_clock __prci_init_clocks_fu740[] = {
+ [PRCI_CLK_COREPLL] = {
+ .name = "corepll",
+ .parent_name = "hfclk",
+ .ops =
[PATCH v4 3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig| 4 +-
drivers/clk/sifive/Makefile | 1 +
drivers/clk/sifive/fu740-prci.c | 122 ++
drivers/clk/sifive/fu740-prci.h | 21 +++
drivers/clk/sifive/sifive-prci.c | 120 +
drivers/clk/sifive/sifive-prci.h | 88 +
include/dt-bindings/clock/sifive-fu740-prci.h | 23
7 files changed, 377 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index ab48cf7e0105..1c14eb20c066 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -13,7 +13,7 @@ config CLK_SIFIVE_PRCI
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in
- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
- enable this driver.
+ FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
+ FU740 SoCs, enable this driver.
endif
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index fe3e2cb4c4d8..2c05798e4ba4 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -2,3 +2,4 @@
obj-y += sifive-prci.o
obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o
+obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu740-prci.o
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
new file mode 100644
index ..3b87e273c3eb
--- /dev/null
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include "sifive-prci.h"
+
+/* PRCI integration data for each WRPLL instance */
+
+static struct __prci_wrpll_data __prci_corepll_data = {
+ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_coreclksel_use_hfclk,
+ .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
+};
+
+static struct __prci_wrpll_data __prci_ddrpll_data = {
+ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_gemgxlpll_data = {
+ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_dvfscorepll_data = {
+ .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_corepllsel_use_corepll,
+ .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
+};
+
+static struct __prci_wrpll_data __prci_hfpclkpll_data = {
+ .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
+ .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
+ .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
+};
+
+static struct __prci_wrpll_data __prci_cltxpll_data = {
+ .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
+};
+
+/* Linux clock framework integration */
+
+static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
+ .set_rate = sifive_prci_wrpll_set_rate,
+ .round_rate = sifive_prci_wrpll_round_rate,
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
+ .recalc_rate = sifive_prci_tlclksel_recalc_rate,
+};
+
+static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
+ .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
+};
+
+/* List of clock controls provided by the PRCI */
+struct __prci_clock __prci_init_clocks_fu740[] = {
+ [PRCI_CLK_COREPLL] = {
+ .name = "corepll",
+ .parent_name = "hfclk",
+ .ops = _fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_corepll_data,
+ },
+ [PRCI_CLK_DDRPLL] = {
+ .name = "ddrpll",
+ .parent_name = "hfclk",
+
