Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
Hi Atish,
On Sun, Apr 18, 2021 at 5:37 AM Atish Patra wrote:
>
> On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
> >
> > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> > >
> > > Hi Atish,
> > >
> > > Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
> > > > Add initial DTS for Microchip ICICLE board having only
> > > > essential devices (clocks, sdhci, ethernet, serial, etc).
> > > > The device tree is based on the U-Boot patch.
> > > >
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
> > > >
> > > > Signed-off-by: Atish Patra
> > > > ---
> > > > arch/riscv/boot/dts/Makefile | 1 +
> > > > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72
> > > > .../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
> > > > 4 files changed, 404 insertions(+)
> > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > > > create mode 100644
> > > > arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > > > index 7ffd502e3e7b..fe996b88319e 100644
> > > > --- a/arch/riscv/boot/dts/Makefile
> > > > +++ b/arch/riscv/boot/dts/Makefile
> > > > @@ -1,5 +1,6 @@
> > > > # SPDX-License-Identifier: GPL-2.0
> > > > subdir-y += sifive
> > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > > > +subdir-y += microchip
> > > >
> > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > > > b/arch/riscv/boot/dts/microchip/Makefile
> > > > new file mode 100644
> > > > index ..622b12771fd3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > > > @@ -0,0 +1,2 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> > >
> > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the
> > > following to have the device tree actually builtin the kernel:
> > >
> > > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > > b/arch/riscv/boot/dts/microchip/Makefile
> > > index 622b12771fd3..855c1502d912 100644
> > > --- a/arch/riscv/boot/dts/microchip/Makefile
> > > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > > @@ -1,2 +1,3 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> > > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> > >
> > > Alex
> >
> > Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire,
> > regardless of whether the kernel is XIP or not.
> >
>
> But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel.
> The bootloaders for polarfire is capable of providing a DTB to kernel.
I have hard time seeing an industrial application with a bootloader
mounting a vfat partition to load a device tree file. So there has to
be a less obscure and less time consuming alternative. And if the
mainline kernel doesn't provide it (e. g. in the form of support for
BUILTIN_DTB) it opens up for error prone custom solutions from various
vendors. Is that really what we want?
Best regards,
Vitaly
> If XIP kernel is enabled, the following line in
> arch/riscv/boot/dts/Makefile should take care of things
>
>
> > Best regards,
> >Vitaly
> >
> > > > diff --git
> > > > a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > new file mode 100644
> > > > index ..ec79944065c9
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > @@ -0,0 +1,72 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/* Copyright (c) 2020 Microchip Technology Inc */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include "microchip-mpfs.dtsi"
> > > > +
> > > > +/* Clock frequency (in Hz) of the rtcclk */
> > > > +#define RTCCLK_FREQ 100
> > > > +
> > > > +/ {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + model = "Microchip PolarFire-SoC Icicle Kit";
> > > > + compatible = "microchip,mpfs-icicle-kit";
> > > > +
> > > > + chosen {
> > > > + stdout-path =
> > > > + };
> > > > +
> > > > + cpus {
> > > > + timebase-frequency = ;
> > > > + };
> > > > +
> > > > + memory@8000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x8000 0x0 0x4000>;
> > > > + clocks = < 26>;
> > > > + };
> > > > +
> > > > + soc {
> > > > + };
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > >
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On Sat, Apr 17, 2021 at 8:36 PM Atish Patra wrote:
>
> On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
> >
> > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> > >
> > > Hi Atish,
> > >
> > > Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
> > > > Add initial DTS for Microchip ICICLE board having only
> > > > essential devices (clocks, sdhci, ethernet, serial, etc).
> > > > The device tree is based on the U-Boot patch.
> > > >
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
> > > >
> > > > Signed-off-by: Atish Patra
> > > > ---
> > > > arch/riscv/boot/dts/Makefile | 1 +
> > > > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72
> > > > .../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
> > > > 4 files changed, 404 insertions(+)
> > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > > > create mode 100644
> > > > arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > > > index 7ffd502e3e7b..fe996b88319e 100644
> > > > --- a/arch/riscv/boot/dts/Makefile
> > > > +++ b/arch/riscv/boot/dts/Makefile
> > > > @@ -1,5 +1,6 @@
> > > > # SPDX-License-Identifier: GPL-2.0
> > > > subdir-y += sifive
> > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > > > +subdir-y += microchip
> > > >
> > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > > > b/arch/riscv/boot/dts/microchip/Makefile
> > > > new file mode 100644
> > > > index ..622b12771fd3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > > > @@ -0,0 +1,2 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> > >
> > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the
> > > following to have the device tree actually builtin the kernel:
> > >
> > > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > > b/arch/riscv/boot/dts/microchip/Makefile
> > > index 622b12771fd3..855c1502d912 100644
> > > --- a/arch/riscv/boot/dts/microchip/Makefile
> > > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > > @@ -1,2 +1,3 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> > > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> > >
> > > Alex
> >
> > Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire,
> > regardless of whether the kernel is XIP or not.
> >
>
> But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel.
> The bootloaders for polarfire is capable of providing a DTB to kernel.
>
> If XIP kernel is enabled, the following line in
> arch/riscv/boot/dts/Makefile should take care of things
>
(Sorry. The mail was sent by mistake earlier with incomplete response)
Otherwise, we need a similar change for unleashed as well. No ?
>
> > Best regards,
> >Vitaly
> >
> > > > diff --git
> > > > a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > new file mode 100644
> > > > index ..ec79944065c9
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > > @@ -0,0 +1,72 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/* Copyright (c) 2020 Microchip Technology Inc */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include "microchip-mpfs.dtsi"
> > > > +
> > > > +/* Clock frequency (in Hz) of the rtcclk */
> > > > +#define RTCCLK_FREQ 100
> > > > +
> > > > +/ {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + model = "Microchip PolarFire-SoC Icicle Kit";
> > > > + compatible = "microchip,mpfs-icicle-kit";
> > > > +
> > > > + chosen {
> > > > + stdout-path =
> > > > + };
> > > > +
> > > > + cpus {
> > > > + timebase-frequency = ;
> > > > + };
> > > > +
> > > > + memory@8000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x8000 0x0 0x4000>;
> > > > + clocks = < 26>;
> > > > + };
> > > > +
> > > > + soc {
> > > > + };
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > + {
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > + {
> > > > + phy-mode = "sgmii";
> > > > + phy-handle = <>;
> > > > +
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
>
> On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> >
> > Hi Atish,
> >
> > Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
> > > Add initial DTS for Microchip ICICLE board having only
> > > essential devices (clocks, sdhci, ethernet, serial, etc).
> > > The device tree is based on the U-Boot patch.
> > >
> > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
> > >
> > > Signed-off-by: Atish Patra
> > > ---
> > > arch/riscv/boot/dts/Makefile | 1 +
> > > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > > .../microchip/microchip-mpfs-icicle-kit.dts | 72
> > > .../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
> > > 4 files changed, 404 insertions(+)
> > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > > create mode 100644
> > > arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > > index 7ffd502e3e7b..fe996b88319e 100644
> > > --- a/arch/riscv/boot/dts/Makefile
> > > +++ b/arch/riscv/boot/dts/Makefile
> > > @@ -1,5 +1,6 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > subdir-y += sifive
> > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > > +subdir-y += microchip
> > >
> > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > > b/arch/riscv/boot/dts/microchip/Makefile
> > > new file mode 100644
> > > index ..622b12771fd3
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > > @@ -0,0 +1,2 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> >
> > I'm playing (or trying to...) with XIP_KERNEL and I had to add the
> > following to have the device tree actually builtin the kernel:
> >
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > index 622b12771fd3..855c1502d912 100644
> > --- a/arch/riscv/boot/dts/microchip/Makefile
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -1,2 +1,3 @@
> > # SPDX-License-Identifier: GPL-2.0
> > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> >
> > Alex
>
> Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire,
> regardless of whether the kernel is XIP or not.
>
But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel.
The bootloaders for polarfire is capable of providing a DTB to kernel.
If XIP kernel is enabled, the following line in
arch/riscv/boot/dts/Makefile should take care of things
> Best regards,
>Vitaly
>
> > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > new file mode 100644
> > > index ..ec79944065c9
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > > @@ -0,0 +1,72 @@
> > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > +/* Copyright (c) 2020 Microchip Technology Inc */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "microchip-mpfs.dtsi"
> > > +
> > > +/* Clock frequency (in Hz) of the rtcclk */
> > > +#define RTCCLK_FREQ 100
> > > +
> > > +/ {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + model = "Microchip PolarFire-SoC Icicle Kit";
> > > + compatible = "microchip,mpfs-icicle-kit";
> > > +
> > > + chosen {
> > > + stdout-path =
> > > + };
> > > +
> > > + cpus {
> > > + timebase-frequency = ;
> > > + };
> > > +
> > > + memory@8000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x8000 0x0 0x4000>;
> > > + clocks = < 26>;
> > > + };
> > > +
> > > + soc {
> > > + };
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > +};
> > > +
> > > + {
> > > + phy-mode = "sgmii";
> > > + phy-handle = <>;
> > > + phy0: ethernet-phy@8 {
> > > + reg = <8>;
> > > + ti,fifo-depth = <0x01>;
> > > + };
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > + phy-mode = "sgmii";
> > > + phy-handle = <>;
> > > + phy1: ethernet-phy@9 {
> > > + reg = <9>;
> > > + ti,fifo-depth = <0x01>;
> > > + };
> > > +};
> > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > >
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
>
> Hi Atish,
>
> Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
> > Add initial DTS for Microchip ICICLE board having only
> > essential devices (clocks, sdhci, ethernet, serial, etc).
> > The device tree is based on the U-Boot patch.
> >
> > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > .../microchip/microchip-mpfs-icicle-kit.dts | 72
> > .../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
> > 4 files changed, 404 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644
> > arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index 7ffd502e3e7b..fe996b88319e 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index ..622b12771fd3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
>
> I'm playing (or trying to...) with XIP_KERNEL and I had to add the
> following to have the device tree actually builtin the kernel:
>
> diff --git a/arch/riscv/boot/dts/microchip/Makefile
> b/arch/riscv/boot/dts/microchip/Makefile
> index 622b12771fd3..855c1502d912 100644
> --- a/arch/riscv/boot/dts/microchip/Makefile
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
>
> Alex
Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire,
regardless of whether the kernel is XIP or not.
Best regards,
Vitaly
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > new file mode 100644
> > index ..ec79944065c9
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,72 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "microchip-mpfs.dtsi"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + chosen {
> > + stdout-path =
> > + };
> > +
> > + cpus {
> > + timebase-frequency = ;
> > + };
> > +
> > + memory@8000 {
> > + device_type = "memory";
> > + reg = <0x0 0x8000 0x0 0x4000>;
> > + clocks = < 26>;
> > + };
> > +
> > + soc {
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + phy-mode = "sgmii";
> > + phy-handle = <>;
> > + phy0: ethernet-phy@8 {
> > + reg = <8>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
> > + phy-mode = "sgmii";
> > + phy-handle = <>;
> > + phy1: ethernet-phy@9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > +};
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > new file mode 100644
> > index ..b9819570a7d1
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > @@ -0,0 +1,329 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip MPFS Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + chosen {
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > +
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
Hi Atish,
Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-mpfs-icicle-kit.dts | 72
.../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
4 files changed, 404 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 7ffd502e3e7b..fe996b88319e 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..622b12771fd3
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
I'm playing (or trying to...) with XIP_KERNEL and I had to add the
following to have the device tree actually builtin the kernel:
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
index 622b12771fd3..855c1502d912 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
Alex
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
new file mode 100644
index ..ec79944065c9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "microchip-mpfs.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ timebase-frequency = ;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x0 0x8000 0x0 0x4000>;
+ clocks = < 26>;
+ };
+
+ soc {
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ phy-mode = "sgmii";
+ phy-handle = <>;
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x01>;
+ };
+};
+
+ {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ ti,fifo-depth = <0x01>;
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
new file mode 100644
index ..b9819570a7d1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On Thu, Mar 4, 2021 at 8:48 PM Atish Patra wrote: > > Add initial DTS for Microchip ICICLE board having only > essential devices (clocks, sdhci, ethernet, serial, etc). > The device tree is based on the U-Boot patch. > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/ > > Signed-off-by: Atish Patra > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile| 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 > .../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++ > 4 files changed, 404 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 > arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > Reviewed-by: Bin Meng
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, 2021-03-09 at 13:30 +, lewis.ha...@microchip.com wrote:
>
>
> From: Ben Dooks
> Sent: Tuesday, March 9, 2021 10:56 AM
> To: Atish Patra ; linux-kernel@vger.kernel.org <
> linux-kernel@vger.kernel.org>
> Cc: Albert Ou ; Alistair Francis <
> alistair.fran...@wdc.com>; Anup Patel ; Björn
> Töpel ; devicet...@vger.kernel.org <
> devicet...@vger.kernel.org>; linux-ri...@lists.infradead.org <
> linux-ri...@lists.infradead.org>; Palmer Dabbelt
> ; Paul Walmsley ; Rob
> Herring < robh...@kernel.org>; Conor Dooley - M52691 <
> conor.doo...@microchip.com>; Daire McNamara - X61553 <
> daire.mcnam...@microchip.com>; Ivan Griffin - X61451 <
> ivan.grif...@microchip.com>; Lewis Hanly - M34782 <
> lewis.ha...@microchip.com>
> Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE
> board
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On 03/03/2021 20:02, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devices (clocks, sdhci, ethernet, serial, etc).
> > The device tree is based on the U-Boot patch.
> >
> > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-mpfs-icicle-kit.dts | 72
> > .../boot/dts/microchip/microchip-mpfs.dtsi | 329
> > ++
> > 4 files changed, 404 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-
> > icicle-kit.dts
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-
> > mpfs.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index 7ffd502e3e7b..fe996b88319e 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index ..622b12771fd3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-
> > kit.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> > kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> > kit.dts
> > new file mode 100644
> > index ..ec79944065c9
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,72 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "microchip-mpfs.dtsi"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + chosen {
> > + stdout-path =
> > + };
> > +
> > + cpus {
> > + timebase-frequency = ;
> > + };
> > +
> > + memory@8000 {
> > + device_type = "memory";
> > + reg = <0x0 0x8000 0x0 0x4000>;
> > + clocks = < 26>;
> > + };
> > +
>
> The latest Microchip releases have two memory nodes to provide the
> full 2GiB of memory space.
> > > For this release we want to leave it at 1GB, wip memory remapping
> > > with the newer releases.
>
Thanks for the clarification. For some reason, your reply did not land
in the mailing lists.
> > + soc {
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + phy-mode = "sgmii";
> > + phy-handle = <>;
> > + phy0: ethernet-phy@8 {
> > + reg = <8>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
> > + phy-mode = "sgmii";
> > + phy-handle = <>;
> > + phy1: ethernet-phy@9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > +};
>
>
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
--
Regards,
Atish
Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On 03/03/2021 20:02, Atish Patra wrote:
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-mpfs-icicle-kit.dts | 72
.../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
4 files changed, 404 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 7ffd502e3e7b..fe996b88319e 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..622b12771fd3
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
new file mode 100644
index ..ec79944065c9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "microchip-mpfs.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ timebase-frequency = ;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x0 0x8000 0x0 0x4000>;
+ clocks = < 26>;
+ };
+
The latest Microchip releases have two memory nodes to provide the
full 2GiB of memory space.
+ soc {
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ phy-mode = "sgmii";
+ phy-handle = <>;
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x01>;
+ };
+};
+
+ {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ ti,fifo-depth = <0x01>;
+ };
+};
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
[PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-mpfs-icicle-kit.dts | 72
.../boot/dts/microchip/microchip-mpfs.dtsi| 329 ++
4 files changed, 404 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 7ffd502e3e7b..fe996b88319e 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..622b12771fd3
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
new file mode 100644
index ..ec79944065c9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "microchip-mpfs.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ timebase-frequency = ;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x0 0x8000 0x0 0x4000>;
+ clocks = < 26>;
+ };
+
+ soc {
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ phy-mode = "sgmii";
+ phy-handle = <>;
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x01>;
+ };
+};
+
+ {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ ti,fifo-depth = <0x01>;
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
new file mode 100644
index ..b9819570a7d1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+
