Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-19 Thread icenowy 

在 2017-08-19 17:11，Chen-Yu Tsai 写道：

On Tue, Aug 15, 2017 at 4:52 PM,   wrote:

在 2017-08-15 13:55，Icenowy Zheng 写道：


Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290
+
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

[...]

+static void __init sun8i_r40_ccu_setup(struct device_node *node)
+{
+   void __iomem *reg;
+   u32 val;
+
+   reg = of_io_request_and_map(node, 0, 
of_node_full_name(node));

+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n",
+  of_node_full_name(node));
+   return;
+   }
+
+   /* Force the PLL-Audio-1x divider to 4 */
+   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
+   val &= ~GENMASK(19, 16);
+   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
+
+   /* Force PLL-MIPI to MIPI mode */
+   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
+   val &= ~BIT(16);
+   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
+
+   /* Force OHCI 12M parent to 0 */


Clarified the comment as

Force OHCI 12M parent to 12M divided from 48M


+   val = readl(reg + SUN8I_R40_USB_CLK_REG);
+   val &= ~GENMASK(20, 6);



Sorry but I think this line should be:

val &= ~GENMASK(25, 20);

I didn't understand GENMASK well...


Fixed and applied. Thanks!


Thanks!



ChenYu

Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-19 Thread icenowy 

在 2017-08-19 17:11，Chen-Yu Tsai 写道：

On Tue, Aug 15, 2017 at 4:52 PM,   wrote:

在 2017-08-15 13:55，Icenowy Zheng 写道：


Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290
+
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

[...]

+static void __init sun8i_r40_ccu_setup(struct device_node *node)
+{
+   void __iomem *reg;
+   u32 val;
+
+   reg = of_io_request_and_map(node, 0, 
of_node_full_name(node));

+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n",
+  of_node_full_name(node));
+   return;
+   }
+
+   /* Force the PLL-Audio-1x divider to 4 */
+   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
+   val &= ~GENMASK(19, 16);
+   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
+
+   /* Force PLL-MIPI to MIPI mode */
+   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
+   val &= ~BIT(16);
+   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
+
+   /* Force OHCI 12M parent to 0 */


Clarified the comment as

Force OHCI 12M parent to 12M divided from 48M


+   val = readl(reg + SUN8I_R40_USB_CLK_REG);
+   val &= ~GENMASK(20, 6);



Sorry but I think this line should be:

val &= ~GENMASK(25, 20);

I didn't understand GENMASK well...


Fixed and applied. Thanks!


Thanks!



ChenYu

Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-19 Thread Chen-Yu Tsai 
On Tue, Aug 15, 2017 at 4:52 PM,   wrote:
> 在 2017-08-15 13:55，Icenowy Zheng 写道：
>>
>> Allwinner R40 SoC have a clock controller module in the style of the
>> SoCs beyond sun6i, however, it's more rich and complex.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>> Changes in v5:
>> - Added TODO's for PLL constraints.
>> - Forced OHCI12M mux to 0.
>> - Changed "adda" clock to "codec" to be consistent with "bus-codec".
>> - Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
>> - Added PLL_CPU gate notifier.
>> Changes in v4:
>> - Removed usb-ohci-12M mux clocks.
>> - Removed unused (and not in user manual) adda-4x clock.
>> - Implemented proper SATA PLL system.
>> - Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
>> - Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
>> - Added missing RST_DRAM.
>> - Several clock post/pre-dividers and constraints fixes.
>> Changes in v3:
>> - Rebased on current linux-next.
>> Changes in v2:
>> - Fixes according to the SoC's user manual.
>>
>>  drivers/clk/sunxi-ng/Kconfig  |5 +
>>  drivers/clk/sunxi-ng/Makefile |1 +
>>  drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290
>> +
>>  drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
>>  include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
>>  include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
>>  6 files changed, 1682 insertions(+)
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
>>  create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
>>  create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
>>
>> [...]
>>
>> +static void __init sun8i_r40_ccu_setup(struct device_node *node)
>> +{
>> +   void __iomem *reg;
>> +   u32 val;
>> +
>> +   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
>> +   if (IS_ERR(reg)) {
>> +   pr_err("%s: Could not map the clock registers\n",
>> +  of_node_full_name(node));
>> +   return;
>> +   }
>> +
>> +   /* Force the PLL-Audio-1x divider to 4 */
>> +   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
>> +   val &= ~GENMASK(19, 16);
>> +   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
>> +
>> +   /* Force PLL-MIPI to MIPI mode */
>> +   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
>> +   val &= ~BIT(16);
>> +   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
>> +
>> +   /* Force OHCI 12M parent to 0 */

Clarified the comment as

Force OHCI 12M parent to 12M divided from 48M

>> +   val = readl(reg + SUN8I_R40_USB_CLK_REG);
>> +   val &= ~GENMASK(20, 6);
>
>
> Sorry but I think this line should be:
>
> val &= ~GENMASK(25, 20);
>
> I didn't understand GENMASK well...

Fixed and applied. Thanks!

ChenYu

Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-19 Thread Chen-Yu Tsai 
On Tue, Aug 15, 2017 at 4:52 PM,   wrote:
> 在 2017-08-15 13:55，Icenowy Zheng 写道：
>>
>> Allwinner R40 SoC have a clock controller module in the style of the
>> SoCs beyond sun6i, however, it's more rich and complex.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>> Changes in v5:
>> - Added TODO's for PLL constraints.
>> - Forced OHCI12M mux to 0.
>> - Changed "adda" clock to "codec" to be consistent with "bus-codec".
>> - Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
>> - Added PLL_CPU gate notifier.
>> Changes in v4:
>> - Removed usb-ohci-12M mux clocks.
>> - Removed unused (and not in user manual) adda-4x clock.
>> - Implemented proper SATA PLL system.
>> - Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
>> - Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
>> - Added missing RST_DRAM.
>> - Several clock post/pre-dividers and constraints fixes.
>> Changes in v3:
>> - Rebased on current linux-next.
>> Changes in v2:
>> - Fixes according to the SoC's user manual.
>>
>>  drivers/clk/sunxi-ng/Kconfig  |5 +
>>  drivers/clk/sunxi-ng/Makefile |1 +
>>  drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290
>> +
>>  drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
>>  include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
>>  include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
>>  6 files changed, 1682 insertions(+)
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
>>  create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
>>  create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
>>
>> [...]
>>
>> +static void __init sun8i_r40_ccu_setup(struct device_node *node)
>> +{
>> +   void __iomem *reg;
>> +   u32 val;
>> +
>> +   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
>> +   if (IS_ERR(reg)) {
>> +   pr_err("%s: Could not map the clock registers\n",
>> +  of_node_full_name(node));
>> +   return;
>> +   }
>> +
>> +   /* Force the PLL-Audio-1x divider to 4 */
>> +   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
>> +   val &= ~GENMASK(19, 16);
>> +   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
>> +
>> +   /* Force PLL-MIPI to MIPI mode */
>> +   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
>> +   val &= ~BIT(16);
>> +   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
>> +
>> +   /* Force OHCI 12M parent to 0 */

Clarified the comment as

Force OHCI 12M parent to 12M divided from 48M

>> +   val = readl(reg + SUN8I_R40_USB_CLK_REG);
>> +   val &= ~GENMASK(20, 6);
>
>
> Sorry but I think this line should be:
>
> val &= ~GENMASK(25, 20);
>
> I didn't understand GENMASK well...

Fixed and applied. Thanks!

ChenYu

Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-15 Thread icenowy 

在 2017-08-15 13:55，Icenowy Zheng 写道：

Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290 
+

 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

[...]
+static void __init sun8i_r40_ccu_setup(struct device_node *node)
+{
+   void __iomem *reg;
+   u32 val;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n",
+  of_node_full_name(node));
+   return;
+   }
+
+   /* Force the PLL-Audio-1x divider to 4 */
+   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
+   val &= ~GENMASK(19, 16);
+   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
+
+   /* Force PLL-MIPI to MIPI mode */
+   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
+   val &= ~BIT(16);
+   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
+
+   /* Force OHCI 12M parent to 0 */
+   val = readl(reg + SUN8I_R40_USB_CLK_REG);
+   val &= ~GENMASK(20, 6);


Sorry but I think this line should be:

val &= ~GENMASK(25, 20);

I didn't understand GENMASK well...


+   writel(val, reg + SUN8I_R40_USB_CLK_REG);
+
+   sunxi_ccu_probe(node, reg, _r40_ccu_desc);
+
+   /* Gate then ungate PLL CPU after any rate changes */
+   ccu_pll_notifier_register(_r40_pll_cpu_nb);
+
+   /* Reparent CPU during PLL CPU rate changes */
+   ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
+ _r40_cpu_nb);
+}
[...]

Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-15 Thread icenowy 

在 2017-08-15 13:55，Icenowy Zheng 写道：

Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290 
+

 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

[...]
+static void __init sun8i_r40_ccu_setup(struct device_node *node)
+{
+   void __iomem *reg;
+   u32 val;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n",
+  of_node_full_name(node));
+   return;
+   }
+
+   /* Force the PLL-Audio-1x divider to 4 */
+   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
+   val &= ~GENMASK(19, 16);
+   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
+
+   /* Force PLL-MIPI to MIPI mode */
+   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
+   val &= ~BIT(16);
+   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
+
+   /* Force OHCI 12M parent to 0 */
+   val = readl(reg + SUN8I_R40_USB_CLK_REG);
+   val &= ~GENMASK(20, 6);


Sorry but I think this line should be:

val &= ~GENMASK(25, 20);

I didn't understand GENMASK well...


+   writel(val, reg + SUN8I_R40_USB_CLK_REG);
+
+   sunxi_ccu_probe(node, reg, _r40_ccu_desc);
+
+   /* Gate then ungate PLL CPU after any rate changes */
+   ccu_pll_notifier_register(_r40_pll_cpu_nb);
+
+   /* Reparent CPU during PLL CPU rate changes */
+   ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
+ _r40_cpu_nb);
+}
[...]

[PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-14 Thread Icenowy Zheng 
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 7342928c35cd..7a360737fe3c 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -48,6 +48,11 @@ config SUN8I_V3S_CCU
 config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
 
+config SUN8I_R40_CCU
+   bool "Support for the Allwinner R40 CCU"
+   default MACH_SUN8I
+   depends on MACH_SUN8I || COMPILE_TEST
+
 config SUN9I_A80_CCU
bool "Support for the Allwinner A80 CCU"
default MACH_SUN9I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 45a5910379a5..b1267fe68a8f 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)+= ccu-sun8i-h3.o
 obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
 obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o
 obj-$(CONFIG_SUN8I_R_CCU)  += ccu-sun8i-r.o
+obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
new file mode 100644
index ..abb4569d3886
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -0,0 +1,1290 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-r40.h"
+
+/* TODO: The result of N*K is required to be in [10, 88] range. */
+static struct ccu_nkmp pll_cpu_clk = {
+   .enable = BIT(31),
+   .lock   = BIT(28),
+   .n  = _SUNXI_CCU_MULT(8, 5),
+   .k  = _SUNXI_CCU_MULT(4, 2),
+   .m  = _SUNXI_CCU_DIV(0, 2),
+   .p  = _SUNXI_CCU_DIV_MAX(16, 2, 4),
+   .common = {
+   .reg= 0x000,
+   .hw.init= CLK_HW_INIT("pll-cpu",
+ "osc24M",
+ _nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+   },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN8I_R40_PLL_AUDIO_REG0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+  "osc24M", 0x008,
+  8, 7,/* N */
+  0, 5,

[PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-14 Thread Icenowy Zheng 
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 7342928c35cd..7a360737fe3c 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -48,6 +48,11 @@ config SUN8I_V3S_CCU
 config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
 
+config SUN8I_R40_CCU
+   bool "Support for the Allwinner R40 CCU"
+   default MACH_SUN8I
+   depends on MACH_SUN8I || COMPILE_TEST
+
 config SUN9I_A80_CCU
bool "Support for the Allwinner A80 CCU"
default MACH_SUN9I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 45a5910379a5..b1267fe68a8f 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)+= ccu-sun8i-h3.o
 obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
 obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o
 obj-$(CONFIG_SUN8I_R_CCU)  += ccu-sun8i-r.o
+obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
new file mode 100644
index ..abb4569d3886
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -0,0 +1,1290 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-r40.h"
+
+/* TODO: The result of N*K is required to be in [10, 88] range. */
+static struct ccu_nkmp pll_cpu_clk = {
+   .enable = BIT(31),
+   .lock   = BIT(28),
+   .n  = _SUNXI_CCU_MULT(8, 5),
+   .k  = _SUNXI_CCU_MULT(4, 2),
+   .m  = _SUNXI_CCU_DIV(0, 2),
+   .p  = _SUNXI_CCU_DIV_MAX(16, 2, 4),
+   .common = {
+   .reg= 0x000,
+   .hw.init= CLK_HW_INIT("pll-cpu",
+ "osc24M",
+ _nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+   },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN8I_R40_PLL_AUDIO_REG0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+  "osc24M", 0x008,
+  8, 7,/* N */
+  0, 5,/* M */
+