subject:"\[PATCH v5\] mmc\: dw_mmc\-k3\: add sd support for hi3660"

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-24 Thread liwei (CM)

Hi,all

Sorry to bother you, could you spare some time to help review patch v6 that I 
sended. Would you please give us your opinion?

Thnak you very much.


-邮件原件-
发件人: liwei (CM) 
发送时间: 2017年7月6日 15:03
收件人: 'Guodong Xu'; Jaehoon Chung
抄送: Ulf Hansson; adrian.hun...@intel.com; Shawn Lin; 
wsa+rene...@sang-engineering.com; hkallwe...@gmail.com; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
主题: 答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

Hi, Jaehoon
Thank you for your advice during your busy schedule, 1."Need the patch for 
adding "hi3660-dw-mshc" compatible  
Documentation/devicetree/bindings/k3-dw-mshc.txt"
This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1]；need 
this one more?

2. And added the minor comments.
Iwill fix them in patch v6.

Thank you very much.


-邮件原件-
发件人: Guodong Xu [mailto:guodong...@linaro.org]
发送时间: 2017年7月6日 14:45
收件人: Jaehoon Chung; liwei (CM)
抄送: Ulf Hansson; adrian.hun...@intel.com; Shawn Lin; 
wsa+rene...@sang-engineering.com; hkallwe...@gmail.com; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

On Thu, Jul 6, 2017 at 1:13 PM, Jaehoon Chung <jh80.ch...@samsung.com> wrote:
> Hi,
>
> To Guodong, if you can forward this to Li Wei, plz do it. Sorry.
>

Sure. Put Li Wei in cc.
And add my response.

> On 07/03/2017 10:06 AM, liwei wrote:
>>
>> Add sd card support for hi3660 soc
>
> Need the patch for adding "hi3660-dw-mshc" compatible 
> Documentation/devicetree/bindings/k3-dw-mshc.txt
>
> And added the minor comments.
>

Hi, Jaehoo,

This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1], and in 
Linus' master branch [2], will be in mainline v4.13-rc's.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt?h=next-20170706
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

-Guodong

>>
>> Major changes in v3:
>>  - solve review comments from Heiner Kallweit.
>>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>>*use usleep_range() replace udelay() and mdelay().
>>
>> Major changes in v4:
>>  - solve review comments from Jaehoon Chung.
>>*move common register for dwmmc controller to dwmmc header file.
>>*modify definitions type of some register variables.
>>*get rid of the magic numbers.
>>
>> Major changes in v5:
>>  - further improve coding style.
>> ---
>>  drivers/mmc/host/dw_mmc-k3.c | 315 
>> +++
>>  drivers/mmc/host/dw_mmc.h|   2 +
>>  2 files changed, 317 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-k3.c 
>> b/drivers/mmc/host/dw_mmc-k3.c index e38fb0020bb1..a28eb8c7da82
>> 100644
>> --- a/drivers/mmc/host/dw_mmc-k3.c
>> +++ b/drivers/mmc/host/dw_mmc-k3.c
>> @@ -8,6 +8,8 @@
>>   * (at your option) any later version.
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -28,7 +30,38 @@
>>  #define AO_SCTRL_SEL18   BIT(10)
>>  #define AO_SCTRL_CTRL3   0x40C
>>
>> +#define DWMMC_SDIO_ID 2
>> +
>> +#define SOC_SCTRL_SCPERCTRL5(0x314)
>> +#define SDCARD_IO_SEL18 BIT(2)
>> +
>> +#define SDCARD_RD_THRESHOLD  (512)
>> +
>> +#define GENCLK_DIV (7)
>> +
>> +#define GPIO_CLK_ENABLE   BIT(16)
>> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
>> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
>> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
>> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
>> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
>> +
>> +#define TIMING_MODE 3
>> +#define TIMING_CFG_NUM 10
>> +
>> +#define PULL_DOWN BIT(1)
>> +#define PULL_UP   BIT(0)
>> +
>> +#define NUM_PHASES (40)
>> +
>> +#define ENABLE_SHIFT_MIN_SMPL (4)
>> +#define ENABLE_SHIFT_MAX_SMPL (12)
>> +#define USE_DLY_MIN_SMPL (11)
>> +#define USE_DLY_MAX_SMPL (14)
>> +
>>  struct k3_priv {
>> + int ctrl_id;
>> + u32 cur_speed;
>>   struct regmap   *reg;
>>  };
>>
>> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>>   0
>>  };
>&g

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-24 Thread liwei (CM)

Hi,all

Sorry to bother you, could you spare some time to help review patch v6 that I 
sended. Would you please give us your opinion?

Thnak you very much.


-邮件原件-
发件人: liwei (CM) 
发送时间: 2017年7月6日 15:03
收件人: 'Guodong Xu'; Jaehoon Chung
抄送: Ulf Hansson; adrian.hun...@intel.com; Shawn Lin; 
wsa+rene...@sang-engineering.com; hkallwe...@gmail.com; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
主题: 答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

Hi, Jaehoon
Thank you for your advice during your busy schedule, 1."Need the patch for 
adding "hi3660-dw-mshc" compatible  
Documentation/devicetree/bindings/k3-dw-mshc.txt"
This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1]；need 
this one more?

2. And added the minor comments.
Iwill fix them in patch v6.

Thank you very much.


-邮件原件-
发件人: Guodong Xu [mailto:guodong...@linaro.org]
发送时间: 2017年7月6日 14:45
收件人: Jaehoon Chung; liwei (CM)
抄送: Ulf Hansson; adrian.hun...@intel.com; Shawn Lin; 
wsa+rene...@sang-engineering.com; hkallwe...@gmail.com; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

On Thu, Jul 6, 2017 at 1:13 PM, Jaehoon Chung  wrote:
> Hi,
>
> To Guodong, if you can forward this to Li Wei, plz do it. Sorry.
>

Sure. Put Li Wei in cc.
And add my response.

> On 07/03/2017 10:06 AM, liwei wrote:
>>
>> Add sd card support for hi3660 soc
>
> Need the patch for adding "hi3660-dw-mshc" compatible 
> Documentation/devicetree/bindings/k3-dw-mshc.txt
>
> And added the minor comments.
>

Hi, Jaehoo,

This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1], and in 
Linus' master branch [2], will be in mainline v4.13-rc's.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt?h=next-20170706
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

-Guodong

>>
>> Major changes in v3:
>>  - solve review comments from Heiner Kallweit.
>>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>>*use usleep_range() replace udelay() and mdelay().
>>
>> Major changes in v4:
>>  - solve review comments from Jaehoon Chung.
>>*move common register for dwmmc controller to dwmmc header file.
>>*modify definitions type of some register variables.
>>*get rid of the magic numbers.
>>
>> Major changes in v5:
>>  - further improve coding style.
>> ---
>>  drivers/mmc/host/dw_mmc-k3.c | 315 
>> +++
>>  drivers/mmc/host/dw_mmc.h|   2 +
>>  2 files changed, 317 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-k3.c 
>> b/drivers/mmc/host/dw_mmc-k3.c index e38fb0020bb1..a28eb8c7da82
>> 100644
>> --- a/drivers/mmc/host/dw_mmc-k3.c
>> +++ b/drivers/mmc/host/dw_mmc-k3.c
>> @@ -8,6 +8,8 @@
>>   * (at your option) any later version.
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -28,7 +30,38 @@
>>  #define AO_SCTRL_SEL18   BIT(10)
>>  #define AO_SCTRL_CTRL3   0x40C
>>
>> +#define DWMMC_SDIO_ID 2
>> +
>> +#define SOC_SCTRL_SCPERCTRL5(0x314)
>> +#define SDCARD_IO_SEL18 BIT(2)
>> +
>> +#define SDCARD_RD_THRESHOLD  (512)
>> +
>> +#define GENCLK_DIV (7)
>> +
>> +#define GPIO_CLK_ENABLE   BIT(16)
>> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
>> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
>> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
>> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
>> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
>> +
>> +#define TIMING_MODE 3
>> +#define TIMING_CFG_NUM 10
>> +
>> +#define PULL_DOWN BIT(1)
>> +#define PULL_UP   BIT(0)
>> +
>> +#define NUM_PHASES (40)
>> +
>> +#define ENABLE_SHIFT_MIN_SMPL (4)
>> +#define ENABLE_SHIFT_MAX_SMPL (12)
>> +#define USE_DLY_MIN_SMPL (11)
>> +#define USE_DLY_MAX_SMPL (14)
>> +
>>  struct k3_priv {
>> + int ctrl_id;
>> + u32 cur_speed;
>>   struct regmap   *reg;
>>  };
>>
>> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>>   0
>>  };
>>
>> +struct hs_timing {
>>

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-06 Thread liwei (CM)

Hi, Jaehoon
Thank you for your advice during your busy schedule,
1."Need the patch for adding "hi3660-dw-mshc" compatible 
 Documentation/devicetree/bindings/k3-dw-mshc.txt"
This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1]；need 
this one more?

2. And added the minor comments.
Iwill fix them in patch v6.

Thank you very much.


-邮件原件-
发件人: Guodong Xu [mailto:guodong...@linaro.org] 
发送时间: 2017年7月6日 14:45
收件人: Jaehoon Chung; liwei (CM)
抄送: Ulf Hansson; adrian.hun...@intel.com; Shawn Lin; 
wsa+rene...@sang-engineering.com; hkallwe...@gmail.com; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

On Thu, Jul 6, 2017 at 1:13 PM, Jaehoon Chung <jh80.ch...@samsung.com> wrote:
> Hi,
>
> To Guodong, if you can forward this to Li Wei, plz do it. Sorry.
>

Sure. Put Li Wei in cc.
And add my response.

> On 07/03/2017 10:06 AM, liwei wrote:
>>
>> Add sd card support for hi3660 soc
>
> Need the patch for adding "hi3660-dw-mshc" compatible 
> Documentation/devicetree/bindings/k3-dw-mshc.txt
>
> And added the minor comments.
>

Hi, Jaehoo,

This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1], and in 
Linus' master branch [2], will be in mainline v4.13-rc's.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt?h=next-20170706
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

-Guodong

>>
>> Major changes in v3:
>>  - solve review comments from Heiner Kallweit.
>>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>>*use usleep_range() replace udelay() and mdelay().
>>
>> Major changes in v4:
>>  - solve review comments from Jaehoon Chung.
>>*move common register for dwmmc controller to dwmmc header file.
>>*modify definitions type of some register variables.
>>*get rid of the magic numbers.
>>
>> Major changes in v5:
>>  - further improve coding style.
>> ---
>>  drivers/mmc/host/dw_mmc-k3.c | 315 
>> +++
>>  drivers/mmc/host/dw_mmc.h|   2 +
>>  2 files changed, 317 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-k3.c 
>> b/drivers/mmc/host/dw_mmc-k3.c index e38fb0020bb1..a28eb8c7da82 
>> 100644
>> --- a/drivers/mmc/host/dw_mmc-k3.c
>> +++ b/drivers/mmc/host/dw_mmc-k3.c
>> @@ -8,6 +8,8 @@
>>   * (at your option) any later version.
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -28,7 +30,38 @@
>>  #define AO_SCTRL_SEL18   BIT(10)
>>  #define AO_SCTRL_CTRL3   0x40C
>>
>> +#define DWMMC_SDIO_ID 2
>> +
>> +#define SOC_SCTRL_SCPERCTRL5(0x314)
>> +#define SDCARD_IO_SEL18 BIT(2)
>> +
>> +#define SDCARD_RD_THRESHOLD  (512)
>> +
>> +#define GENCLK_DIV (7)
>> +
>> +#define GPIO_CLK_ENABLE   BIT(16)
>> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
>> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
>> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
>> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
>> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
>> +
>> +#define TIMING_MODE 3
>> +#define TIMING_CFG_NUM 10
>> +
>> +#define PULL_DOWN BIT(1)
>> +#define PULL_UP   BIT(0)
>> +
>> +#define NUM_PHASES (40)
>> +
>> +#define ENABLE_SHIFT_MIN_SMPL (4)
>> +#define ENABLE_SHIFT_MAX_SMPL (12)
>> +#define USE_DLY_MIN_SMPL (11)
>> +#define USE_DLY_MAX_SMPL (14)
>> +
>>  struct k3_priv {
>> + int ctrl_id;
>> + u32 cur_speed;
>>   struct regmap   *reg;
>>  };
>>
>> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>>   0
>>  };
>>
>> +struct hs_timing {
>> + u32 drv_phase;
>> + u32 smpl_dly;
>> + u32 smpl_phase_max;
>> + u32 smpl_phase_min;
>> +};
>> +
>> +struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
>> + { /* reserved */ },
>> + { /* SD */
>> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
>> + {6, 0,  4,  4,},  /* 1: MMC_HS */
>> + {6, 0,  3,  3,},  /* 2:

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-06 Thread liwei (CM)

Hi, Jaehoon
Thank you for your advice during your busy schedule,
1."Need the patch for adding "hi3660-dw-mshc" compatible 
 Documentation/devicetree/bindings/k3-dw-mshc.txt"
This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1]；need 
this one more?

2. And added the minor comments.
Iwill fix them in patch v6.

Thank you very much.


-邮件原件-
发件人: Guodong Xu [mailto:guodong...@linaro.org] 
发送时间: 2017年7月6日 14:45
收件人: Jaehoon Chung; liwei (CM)
抄送: Ulf Hansson; adrian.hun...@intel.com; Shawn Lin; 
wsa+rene...@sang-engineering.com; hkallwe...@gmail.com; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

On Thu, Jul 6, 2017 at 1:13 PM, Jaehoon Chung  wrote:
> Hi,
>
> To Guodong, if you can forward this to Li Wei, plz do it. Sorry.
>

Sure. Put Li Wei in cc.
And add my response.

> On 07/03/2017 10:06 AM, liwei wrote:
>>
>> Add sd card support for hi3660 soc
>
> Need the patch for adding "hi3660-dw-mshc" compatible 
> Documentation/devicetree/bindings/k3-dw-mshc.txt
>
> And added the minor comments.
>

Hi, Jaehoo,

This "hi3660-dw-mshc" compatible string has been integrated into platform 
maintainer's tree together with dts changes. It's now in linux-next [1], and in 
Linus' master branch [2], will be in mainline v4.13-rc's.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt?h=next-20170706
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

-Guodong

>>
>> Major changes in v3:
>>  - solve review comments from Heiner Kallweit.
>>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>>*use usleep_range() replace udelay() and mdelay().
>>
>> Major changes in v4:
>>  - solve review comments from Jaehoon Chung.
>>*move common register for dwmmc controller to dwmmc header file.
>>*modify definitions type of some register variables.
>>*get rid of the magic numbers.
>>
>> Major changes in v5:
>>  - further improve coding style.
>> ---
>>  drivers/mmc/host/dw_mmc-k3.c | 315 
>> +++
>>  drivers/mmc/host/dw_mmc.h|   2 +
>>  2 files changed, 317 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-k3.c 
>> b/drivers/mmc/host/dw_mmc-k3.c index e38fb0020bb1..a28eb8c7da82 
>> 100644
>> --- a/drivers/mmc/host/dw_mmc-k3.c
>> +++ b/drivers/mmc/host/dw_mmc-k3.c
>> @@ -8,6 +8,8 @@
>>   * (at your option) any later version.
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -28,7 +30,38 @@
>>  #define AO_SCTRL_SEL18   BIT(10)
>>  #define AO_SCTRL_CTRL3   0x40C
>>
>> +#define DWMMC_SDIO_ID 2
>> +
>> +#define SOC_SCTRL_SCPERCTRL5(0x314)
>> +#define SDCARD_IO_SEL18 BIT(2)
>> +
>> +#define SDCARD_RD_THRESHOLD  (512)
>> +
>> +#define GENCLK_DIV (7)
>> +
>> +#define GPIO_CLK_ENABLE   BIT(16)
>> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
>> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
>> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
>> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
>> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
>> +
>> +#define TIMING_MODE 3
>> +#define TIMING_CFG_NUM 10
>> +
>> +#define PULL_DOWN BIT(1)
>> +#define PULL_UP   BIT(0)
>> +
>> +#define NUM_PHASES (40)
>> +
>> +#define ENABLE_SHIFT_MIN_SMPL (4)
>> +#define ENABLE_SHIFT_MAX_SMPL (12)
>> +#define USE_DLY_MIN_SMPL (11)
>> +#define USE_DLY_MAX_SMPL (14)
>> +
>>  struct k3_priv {
>> + int ctrl_id;
>> + u32 cur_speed;
>>   struct regmap   *reg;
>>  };
>>
>> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>>   0
>>  };
>>
>> +struct hs_timing {
>> + u32 drv_phase;
>> + u32 smpl_dly;
>> + u32 smpl_phase_max;
>> + u32 smpl_phase_min;
>> +};
>> +
>> +struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
>> + { /* reserved */ },
>> + { /* SD */
>> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
>> + {6, 0,  4,  4,},  /* 1: MMC_HS */
>> + {6, 0,  3,  3,},  /* 2: SD_HS */
>

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-06 Thread Guodong Xu

On Thu, Jul 6, 2017 at 1:13 PM, Jaehoon Chung  wrote:
> Hi,
>
> To Guodong, if you can forward this to Li Wei, plz do it. Sorry.
>

Sure. Put Li Wei in cc.
And add my response.

> On 07/03/2017 10:06 AM, liwei wrote:
>>
>> Add sd card support for hi3660 soc
>
> Need the patch for adding "hi3660-dw-mshc" compatible 
> Documentation/devicetree/bindings/k3-dw-mshc.txt
>
> And added the minor comments.
>

Hi, Jaehoo,

This "hi3660-dw-mshc" compatible string has been integrated into
platform maintainer's tree together with dts changes. It's now in
linux-next [1], and in Linus' master branch [2], will be in mainline
v4.13-rc's.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt?h=next-20170706
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

-Guodong

>>
>> Major changes in v3:
>>  - solve review comments from Heiner Kallweit.
>>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>>*use usleep_range() replace udelay() and mdelay().
>>
>> Major changes in v4:
>>  - solve review comments from Jaehoon Chung.
>>*move common register for dwmmc controller to dwmmc header file.
>>*modify definitions type of some register variables.
>>*get rid of the magic numbers.
>>
>> Major changes in v5:
>>  - further improve coding style.
>> ---
>>  drivers/mmc/host/dw_mmc-k3.c | 315 
>> +++
>>  drivers/mmc/host/dw_mmc.h|   2 +
>>  2 files changed, 317 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
>> index e38fb0020bb1..a28eb8c7da82 100644
>> --- a/drivers/mmc/host/dw_mmc-k3.c
>> +++ b/drivers/mmc/host/dw_mmc-k3.c
>> @@ -8,6 +8,8 @@
>>   * (at your option) any later version.
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -28,7 +30,38 @@
>>  #define AO_SCTRL_SEL18   BIT(10)
>>  #define AO_SCTRL_CTRL3   0x40C
>>
>> +#define DWMMC_SDIO_ID 2
>> +
>> +#define SOC_SCTRL_SCPERCTRL5(0x314)
>> +#define SDCARD_IO_SEL18 BIT(2)
>> +
>> +#define SDCARD_RD_THRESHOLD  (512)
>> +
>> +#define GENCLK_DIV (7)
>> +
>> +#define GPIO_CLK_ENABLE   BIT(16)
>> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
>> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
>> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
>> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
>> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
>> +
>> +#define TIMING_MODE 3
>> +#define TIMING_CFG_NUM 10
>> +
>> +#define PULL_DOWN BIT(1)
>> +#define PULL_UP   BIT(0)
>> +
>> +#define NUM_PHASES (40)
>> +
>> +#define ENABLE_SHIFT_MIN_SMPL (4)
>> +#define ENABLE_SHIFT_MAX_SMPL (12)
>> +#define USE_DLY_MIN_SMPL (11)
>> +#define USE_DLY_MAX_SMPL (14)
>> +
>>  struct k3_priv {
>> + int ctrl_id;
>> + u32 cur_speed;
>>   struct regmap   *reg;
>>  };
>>
>> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>>   0
>>  };
>>
>> +struct hs_timing {
>> + u32 drv_phase;
>> + u32 smpl_dly;
>> + u32 smpl_phase_max;
>> + u32 smpl_phase_min;
>> +};
>> +
>> +struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
>> + { /* reserved */ },
>> + { /* SD */
>> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
>> + {6, 0,  4,  4,},  /* 1: MMC_HS */
>> + {6, 0,  3,  3,},  /* 2: SD_HS */
>> + {6, 0, 15, 15,},  /* 3: SDR12 */
>> + {6, 0,  2,  2,},  /* 4: SDR25 */
>> + {4, 0, 11,  0,},  /* 5: SDR50 */
>> + {6, 4, 15,  0,},  /* 6: SDR104 */
>> + {0},  /* 7: DDR50 */
>> + {0},  /* 8: DDR52 */
>> + {0},  /* 9: HS200 */
>> + },
>> + { /* SDIO */
>> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
>> + {0},  /* 1: MMC_HS */
>> + {6, 0, 15, 15,},  /* 2: SD_HS */
>> + {6, 0, 15, 15,},  /* 3: SDR12 */
>> + {6, 0,  0,  0,},  /* 4: SDR25 */
>> + {4, 0, 12,  0,},  /* 5: SDR50 */
>> + {5, 4, 15,  0,},  /* 6: SDR104 */
>> + {0},  /* 7: DDR50 */
>> + {0},  /* 8: DDR52 */
>> + {0},  /* 9: HS200 */
>> + }
>> +};
>> +
>>  static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>>  {
>>   int ret;
>> @@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
>>   if (IS_ERR(priv->reg))
>>   priv->reg = NULL;
>>
>> + priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
>> + if (priv->ctrl_id < 0)
>> + priv->ctrl_id = 0;
>> +
>>   host->priv = priv;
>>   return 0;
>>  }
>> @@ -144,7 +216,245 @@ static const struct

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-06 Thread Guodong Xu

On Thu, Jul 6, 2017 at 1:13 PM, Jaehoon Chung  wrote:
> Hi,
>
> To Guodong, if you can forward this to Li Wei, plz do it. Sorry.
>

Sure. Put Li Wei in cc.
And add my response.

> On 07/03/2017 10:06 AM, liwei wrote:
>>
>> Add sd card support for hi3660 soc
>
> Need the patch for adding "hi3660-dw-mshc" compatible 
> Documentation/devicetree/bindings/k3-dw-mshc.txt
>
> And added the minor comments.
>

Hi, Jaehoo,

This "hi3660-dw-mshc" compatible string has been integrated into
platform maintainer's tree together with dts changes. It's now in
linux-next [1], and in Linus' master branch [2], will be in mainline
v4.13-rc's.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt?h=next-20170706
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

-Guodong

>>
>> Major changes in v3:
>>  - solve review comments from Heiner Kallweit.
>>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>>*use usleep_range() replace udelay() and mdelay().
>>
>> Major changes in v4:
>>  - solve review comments from Jaehoon Chung.
>>*move common register for dwmmc controller to dwmmc header file.
>>*modify definitions type of some register variables.
>>*get rid of the magic numbers.
>>
>> Major changes in v5:
>>  - further improve coding style.
>> ---
>>  drivers/mmc/host/dw_mmc-k3.c | 315 
>> +++
>>  drivers/mmc/host/dw_mmc.h|   2 +
>>  2 files changed, 317 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
>> index e38fb0020bb1..a28eb8c7da82 100644
>> --- a/drivers/mmc/host/dw_mmc-k3.c
>> +++ b/drivers/mmc/host/dw_mmc-k3.c
>> @@ -8,6 +8,8 @@
>>   * (at your option) any later version.
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -28,7 +30,38 @@
>>  #define AO_SCTRL_SEL18   BIT(10)
>>  #define AO_SCTRL_CTRL3   0x40C
>>
>> +#define DWMMC_SDIO_ID 2
>> +
>> +#define SOC_SCTRL_SCPERCTRL5(0x314)
>> +#define SDCARD_IO_SEL18 BIT(2)
>> +
>> +#define SDCARD_RD_THRESHOLD  (512)
>> +
>> +#define GENCLK_DIV (7)
>> +
>> +#define GPIO_CLK_ENABLE   BIT(16)
>> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
>> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
>> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
>> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
>> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
>> +
>> +#define TIMING_MODE 3
>> +#define TIMING_CFG_NUM 10
>> +
>> +#define PULL_DOWN BIT(1)
>> +#define PULL_UP   BIT(0)
>> +
>> +#define NUM_PHASES (40)
>> +
>> +#define ENABLE_SHIFT_MIN_SMPL (4)
>> +#define ENABLE_SHIFT_MAX_SMPL (12)
>> +#define USE_DLY_MIN_SMPL (11)
>> +#define USE_DLY_MAX_SMPL (14)
>> +
>>  struct k3_priv {
>> + int ctrl_id;
>> + u32 cur_speed;
>>   struct regmap   *reg;
>>  };
>>
>> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>>   0
>>  };
>>
>> +struct hs_timing {
>> + u32 drv_phase;
>> + u32 smpl_dly;
>> + u32 smpl_phase_max;
>> + u32 smpl_phase_min;
>> +};
>> +
>> +struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
>> + { /* reserved */ },
>> + { /* SD */
>> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
>> + {6, 0,  4,  4,},  /* 1: MMC_HS */
>> + {6, 0,  3,  3,},  /* 2: SD_HS */
>> + {6, 0, 15, 15,},  /* 3: SDR12 */
>> + {6, 0,  2,  2,},  /* 4: SDR25 */
>> + {4, 0, 11,  0,},  /* 5: SDR50 */
>> + {6, 4, 15,  0,},  /* 6: SDR104 */
>> + {0},  /* 7: DDR50 */
>> + {0},  /* 8: DDR52 */
>> + {0},  /* 9: HS200 */
>> + },
>> + { /* SDIO */
>> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
>> + {0},  /* 1: MMC_HS */
>> + {6, 0, 15, 15,},  /* 2: SD_HS */
>> + {6, 0, 15, 15,},  /* 3: SDR12 */
>> + {6, 0,  0,  0,},  /* 4: SDR25 */
>> + {4, 0, 12,  0,},  /* 5: SDR50 */
>> + {5, 4, 15,  0,},  /* 6: SDR104 */
>> + {0},  /* 7: DDR50 */
>> + {0},  /* 8: DDR52 */
>> + {0},  /* 9: HS200 */
>> + }
>> +};
>> +
>>  static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>>  {
>>   int ret;
>> @@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
>>   if (IS_ERR(priv->reg))
>>   priv->reg = NULL;
>>
>> + priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
>> + if (priv->ctrl_id < 0)
>> + priv->ctrl_id = 0;
>> +
>>   host->priv = priv;
>>   return 0;
>>  }
>> @@ -144,7 +216,245 @@ static const struct dw_mci_drv_data hi6220_data = {

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-05 Thread Jaehoon Chung

Hi,

To Guodong, if you can forward this to Li Wei, plz do it. Sorry.

On 07/03/2017 10:06 AM, liwei wrote:
> 
> Add sd card support for hi3660 soc

Need the patch for adding "hi3660-dw-mshc" compatible 
Documentation/devicetree/bindings/k3-dw-mshc.txt

And added the minor comments.

> 
> Major changes in v3:
>  - solve review comments from Heiner Kallweit.
>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>*use usleep_range() replace udelay() and mdelay().
> 
> Major changes in v4:
>  - solve review comments from Jaehoon Chung.
>*move common register for dwmmc controller to dwmmc header file.
>*modify definitions type of some register variables.
>*get rid of the magic numbers.
> 
> Major changes in v5:
>  - further improve coding style.
> ---
>  drivers/mmc/host/dw_mmc-k3.c | 315 
> +++
>  drivers/mmc/host/dw_mmc.h|   2 +
>  2 files changed, 317 insertions(+)
> 
> diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
> index e38fb0020bb1..a28eb8c7da82 100644
> --- a/drivers/mmc/host/dw_mmc-k3.c
> +++ b/drivers/mmc/host/dw_mmc-k3.c
> @@ -8,6 +8,8 @@
>   * (at your option) any later version.
>   */
>  
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -28,7 +30,38 @@
>  #define AO_SCTRL_SEL18   BIT(10)
>  #define AO_SCTRL_CTRL3   0x40C
>  
> +#define DWMMC_SDIO_ID 2
> +
> +#define SOC_SCTRL_SCPERCTRL5(0x314)
> +#define SDCARD_IO_SEL18 BIT(2)
> +
> +#define SDCARD_RD_THRESHOLD  (512)
> +
> +#define GENCLK_DIV (7)
> +
> +#define GPIO_CLK_ENABLE   BIT(16)
> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
> +
> +#define TIMING_MODE 3
> +#define TIMING_CFG_NUM 10
> +
> +#define PULL_DOWN BIT(1)
> +#define PULL_UP   BIT(0)
> +
> +#define NUM_PHASES (40)
> +
> +#define ENABLE_SHIFT_MIN_SMPL (4)
> +#define ENABLE_SHIFT_MAX_SMPL (12)
> +#define USE_DLY_MIN_SMPL (11)
> +#define USE_DLY_MAX_SMPL (14)
> +
>  struct k3_priv {
> + int ctrl_id;
> + u32 cur_speed;
>   struct regmap   *reg;
>  };
>  
> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>   0
>  };
>  
> +struct hs_timing {
> + u32 drv_phase;
> + u32 smpl_dly;
> + u32 smpl_phase_max;
> + u32 smpl_phase_min;
> +};
> +
> +struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
> + { /* reserved */ },
> + { /* SD */
> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
> + {6, 0,  4,  4,},  /* 1: MMC_HS */
> + {6, 0,  3,  3,},  /* 2: SD_HS */
> + {6, 0, 15, 15,},  /* 3: SDR12 */
> + {6, 0,  2,  2,},  /* 4: SDR25 */
> + {4, 0, 11,  0,},  /* 5: SDR50 */
> + {6, 4, 15,  0,},  /* 6: SDR104 */
> + {0},  /* 7: DDR50 */
> + {0},  /* 8: DDR52 */
> + {0},  /* 9: HS200 */
> + },
> + { /* SDIO */
> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
> + {0},  /* 1: MMC_HS */
> + {6, 0, 15, 15,},  /* 2: SD_HS */
> + {6, 0, 15, 15,},  /* 3: SDR12 */
> + {6, 0,  0,  0,},  /* 4: SDR25 */
> + {4, 0, 12,  0,},  /* 5: SDR50 */
> + {5, 4, 15,  0,},  /* 6: SDR104 */
> + {0},  /* 7: DDR50 */
> + {0},  /* 8: DDR52 */
> + {0},  /* 9: HS200 */
> + }
> +};
> +
>  static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>  {
>   int ret;
> @@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
>   if (IS_ERR(priv->reg))
>   priv->reg = NULL;
>  
> + priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
> + if (priv->ctrl_id < 0)
> + priv->ctrl_id = 0;
> +
>   host->priv = priv;
>   return 0;
>  }
> @@ -144,7 +216,245 @@ static const struct dw_mci_drv_data hi6220_data = {
>   .execute_tuning = dw_mci_hi6220_execute_tuning,
>  };
>  
> +static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
> +  int smpl_phase)
> +{
> + u32 drv_phase;
> + u32 smpl_dly;
> + u32 use_smpl_dly = 0;
> + u32 enable_shift = 0;
> + u32 reg_value;
> + int ctrl_id;
> + struct k3_priv *priv;
> +
> + priv = host->priv;
> + ctrl_id = priv->ctrl_id;
> +
> + drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
> + smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
> + if (smpl_phase == -1)
> + smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
> +

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-05 Thread Jaehoon Chung

Hi,

To Guodong, if you can forward this to Li Wei, plz do it. Sorry.

On 07/03/2017 10:06 AM, liwei wrote:
> 
> Add sd card support for hi3660 soc

Need the patch for adding "hi3660-dw-mshc" compatible 
Documentation/devicetree/bindings/k3-dw-mshc.txt

And added the minor comments.

> 
> Major changes in v3:
>  - solve review comments from Heiner Kallweit.
>*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
>*use usleep_range() replace udelay() and mdelay().
> 
> Major changes in v4:
>  - solve review comments from Jaehoon Chung.
>*move common register for dwmmc controller to dwmmc header file.
>*modify definitions type of some register variables.
>*get rid of the magic numbers.
> 
> Major changes in v5:
>  - further improve coding style.
> ---
>  drivers/mmc/host/dw_mmc-k3.c | 315 
> +++
>  drivers/mmc/host/dw_mmc.h|   2 +
>  2 files changed, 317 insertions(+)
> 
> diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
> index e38fb0020bb1..a28eb8c7da82 100644
> --- a/drivers/mmc/host/dw_mmc-k3.c
> +++ b/drivers/mmc/host/dw_mmc-k3.c
> @@ -8,6 +8,8 @@
>   * (at your option) any later version.
>   */
>  
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -28,7 +30,38 @@
>  #define AO_SCTRL_SEL18   BIT(10)
>  #define AO_SCTRL_CTRL3   0x40C
>  
> +#define DWMMC_SDIO_ID 2
> +
> +#define SOC_SCTRL_SCPERCTRL5(0x314)
> +#define SDCARD_IO_SEL18 BIT(2)
> +
> +#define SDCARD_RD_THRESHOLD  (512)
> +
> +#define GENCLK_DIV (7)
> +
> +#define GPIO_CLK_ENABLE   BIT(16)
> +#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
> +#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
> +#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
> +#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
> +#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
> +
> +#define TIMING_MODE 3
> +#define TIMING_CFG_NUM 10
> +
> +#define PULL_DOWN BIT(1)
> +#define PULL_UP   BIT(0)
> +
> +#define NUM_PHASES (40)
> +
> +#define ENABLE_SHIFT_MIN_SMPL (4)
> +#define ENABLE_SHIFT_MAX_SMPL (12)
> +#define USE_DLY_MIN_SMPL (11)
> +#define USE_DLY_MAX_SMPL (14)
> +
>  struct k3_priv {
> + int ctrl_id;
> + u32 cur_speed;
>   struct regmap   *reg;
>  };
>  
> @@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
>   0
>  };
>  
> +struct hs_timing {
> + u32 drv_phase;
> + u32 smpl_dly;
> + u32 smpl_phase_max;
> + u32 smpl_phase_min;
> +};
> +
> +struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
> + { /* reserved */ },
> + { /* SD */
> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
> + {6, 0,  4,  4,},  /* 1: MMC_HS */
> + {6, 0,  3,  3,},  /* 2: SD_HS */
> + {6, 0, 15, 15,},  /* 3: SDR12 */
> + {6, 0,  2,  2,},  /* 4: SDR25 */
> + {4, 0, 11,  0,},  /* 5: SDR50 */
> + {6, 4, 15,  0,},  /* 6: SDR104 */
> + {0},  /* 7: DDR50 */
> + {0},  /* 8: DDR52 */
> + {0},  /* 9: HS200 */
> + },
> + { /* SDIO */
> + {7, 0, 15, 15,},  /* 0: LEGACY 400k */
> + {0},  /* 1: MMC_HS */
> + {6, 0, 15, 15,},  /* 2: SD_HS */
> + {6, 0, 15, 15,},  /* 3: SDR12 */
> + {6, 0,  0,  0,},  /* 4: SDR25 */
> + {4, 0, 12,  0,},  /* 5: SDR50 */
> + {5, 4, 15,  0,},  /* 6: SDR104 */
> + {0},  /* 7: DDR50 */
> + {0},  /* 8: DDR52 */
> + {0},  /* 9: HS200 */
> + }
> +};
> +
>  static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>  {
>   int ret;
> @@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
>   if (IS_ERR(priv->reg))
>   priv->reg = NULL;
>  
> + priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
> + if (priv->ctrl_id < 0)
> + priv->ctrl_id = 0;
> +
>   host->priv = priv;
>   return 0;
>  }
> @@ -144,7 +216,245 @@ static const struct dw_mci_drv_data hi6220_data = {
>   .execute_tuning = dw_mci_hi6220_execute_tuning,
>  };
>  
> +static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
> +  int smpl_phase)
> +{
> + u32 drv_phase;
> + u32 smpl_dly;
> + u32 use_smpl_dly = 0;
> + u32 enable_shift = 0;
> + u32 reg_value;
> + int ctrl_id;
> + struct k3_priv *priv;
> +
> + priv = host->priv;
> + ctrl_id = priv->ctrl_id;
> +
> + drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
> + smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
> + if (smpl_phase == -1)
> + smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
> +

[PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-02 Thread liwei

From: Li Wei 

Add sd card support for hi3660 soc

Signed-off-by: Li Wei 
Signed-off-by: Chen Jun 

Major changes in v3:
 - solve review comments from Heiner Kallweit.
   *use the GENMASK and FIELD_PREP macros replace the bit shift operation.
   *use usleep_range() replace udelay() and mdelay().

Major changes in v4:
 - solve review comments from Jaehoon Chung.
   *move common register for dwmmc controller to dwmmc header file.
   *modify definitions type of some register variables.
   *get rid of the magic numbers.

Major changes in v5:
 - further improve coding style.
---
 drivers/mmc/host/dw_mmc-k3.c | 315 +++
 drivers/mmc/host/dw_mmc.h|   2 +
 2 files changed, 317 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index e38fb0020bb1..a28eb8c7da82 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -8,6 +8,8 @@
  * (at your option) any later version.
  */
 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -28,7 +30,38 @@
 #define AO_SCTRL_SEL18 BIT(10)
 #define AO_SCTRL_CTRL3 0x40C
 
+#define DWMMC_SDIO_ID 2
+
+#define SOC_SCTRL_SCPERCTRL5(0x314)
+#define SDCARD_IO_SEL18 BIT(2)
+
+#define SDCARD_RD_THRESHOLD  (512)
+
+#define GENCLK_DIV (7)
+
+#define GPIO_CLK_ENABLE   BIT(16)
+#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
+#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
+#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
+#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
+#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
+
+#define TIMING_MODE 3
+#define TIMING_CFG_NUM 10
+
+#define PULL_DOWN BIT(1)
+#define PULL_UP   BIT(0)
+
+#define NUM_PHASES (40)
+
+#define ENABLE_SHIFT_MIN_SMPL (4)
+#define ENABLE_SHIFT_MAX_SMPL (12)
+#define USE_DLY_MIN_SMPL (11)
+#define USE_DLY_MAX_SMPL (14)
+
 struct k3_priv {
+   int ctrl_id;
+   u32 cur_speed;
struct regmap   *reg;
 };
 
@@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
0
 };
 
+struct hs_timing {
+   u32 drv_phase;
+   u32 smpl_dly;
+   u32 smpl_phase_max;
+   u32 smpl_phase_min;
+};
+
+struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
+   { /* reserved */ },
+   { /* SD */
+   {7, 0, 15, 15,},  /* 0: LEGACY 400k */
+   {6, 0,  4,  4,},  /* 1: MMC_HS */
+   {6, 0,  3,  3,},  /* 2: SD_HS */
+   {6, 0, 15, 15,},  /* 3: SDR12 */
+   {6, 0,  2,  2,},  /* 4: SDR25 */
+   {4, 0, 11,  0,},  /* 5: SDR50 */
+   {6, 4, 15,  0,},  /* 6: SDR104 */
+   {0},  /* 7: DDR50 */
+   {0},  /* 8: DDR52 */
+   {0},  /* 9: HS200 */
+   },
+   { /* SDIO */
+   {7, 0, 15, 15,},  /* 0: LEGACY 400k */
+   {0},  /* 1: MMC_HS */
+   {6, 0, 15, 15,},  /* 2: SD_HS */
+   {6, 0, 15, 15,},  /* 3: SDR12 */
+   {6, 0,  0,  0,},  /* 4: SDR25 */
+   {4, 0, 12,  0,},  /* 5: SDR50 */
+   {5, 4, 15,  0,},  /* 6: SDR104 */
+   {0},  /* 7: DDR50 */
+   {0},  /* 8: DDR52 */
+   {0},  /* 9: HS200 */
+   }
+};
+
 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 {
int ret;
@@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
if (IS_ERR(priv->reg))
priv->reg = NULL;
 
+   priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
+   if (priv->ctrl_id < 0)
+   priv->ctrl_id = 0;
+
host->priv = priv;
return 0;
 }
@@ -144,7 +216,245 @@ static const struct dw_mci_drv_data hi6220_data = {
.execute_tuning = dw_mci_hi6220_execute_tuning,
 };
 
+static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
+int smpl_phase)
+{
+   u32 drv_phase;
+   u32 smpl_dly;
+   u32 use_smpl_dly = 0;
+   u32 enable_shift = 0;
+   u32 reg_value;
+   int ctrl_id;
+   struct k3_priv *priv;
+
+   priv = host->priv;
+   ctrl_id = priv->ctrl_id;
+
+   drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
+   smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
+   if (smpl_phase == -1)
+   smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
+hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
+
+   switch (timing) {
+   case MMC_TIMING_UHS_SDR104:
+   if (smpl_phase >= USE_DLY_MIN_SMPL &&
+   smpl_phase <= USE_DLY_MAX_SMPL)
+   use_smpl_dly = 1;
+   /* fallthrough */
+   case MMC_TIMING_UHS_SDR50:

[PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

2017-07-02 Thread liwei

From: Li Wei 

Add sd card support for hi3660 soc

Signed-off-by: Li Wei 
Signed-off-by: Chen Jun 

Major changes in v3:
 - solve review comments from Heiner Kallweit.
   *use the GENMASK and FIELD_PREP macros replace the bit shift operation.
   *use usleep_range() replace udelay() and mdelay().

Major changes in v4:
 - solve review comments from Jaehoon Chung.
   *move common register for dwmmc controller to dwmmc header file.
   *modify definitions type of some register variables.
   *get rid of the magic numbers.

Major changes in v5:
 - further improve coding style.
---
 drivers/mmc/host/dw_mmc-k3.c | 315 +++
 drivers/mmc/host/dw_mmc.h|   2 +
 2 files changed, 317 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index e38fb0020bb1..a28eb8c7da82 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -8,6 +8,8 @@
  * (at your option) any later version.
  */
 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -28,7 +30,38 @@
 #define AO_SCTRL_SEL18 BIT(10)
 #define AO_SCTRL_CTRL3 0x40C
 
+#define DWMMC_SDIO_ID 2
+
+#define SOC_SCTRL_SCPERCTRL5(0x314)
+#define SDCARD_IO_SEL18 BIT(2)
+
+#define SDCARD_RD_THRESHOLD  (512)
+
+#define GENCLK_DIV (7)
+
+#define GPIO_CLK_ENABLE   BIT(16)
+#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
+#define GPIO_USE_SAMPLE_DLY_MASK  GENMASK(13, 13)
+#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
+#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
+#define UHS_REG_EXT_SAMPLE_DLY_MASK   GENMASK(30, 26)
+
+#define TIMING_MODE 3
+#define TIMING_CFG_NUM 10
+
+#define PULL_DOWN BIT(1)
+#define PULL_UP   BIT(0)
+
+#define NUM_PHASES (40)
+
+#define ENABLE_SHIFT_MIN_SMPL (4)
+#define ENABLE_SHIFT_MAX_SMPL (12)
+#define USE_DLY_MIN_SMPL (11)
+#define USE_DLY_MAX_SMPL (14)
+
 struct k3_priv {
+   int ctrl_id;
+   u32 cur_speed;
struct regmap   *reg;
 };
 
@@ -38,6 +71,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
0
 };
 
+struct hs_timing {
+   u32 drv_phase;
+   u32 smpl_dly;
+   u32 smpl_phase_max;
+   u32 smpl_phase_min;
+};
+
+struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
+   { /* reserved */ },
+   { /* SD */
+   {7, 0, 15, 15,},  /* 0: LEGACY 400k */
+   {6, 0,  4,  4,},  /* 1: MMC_HS */
+   {6, 0,  3,  3,},  /* 2: SD_HS */
+   {6, 0, 15, 15,},  /* 3: SDR12 */
+   {6, 0,  2,  2,},  /* 4: SDR25 */
+   {4, 0, 11,  0,},  /* 5: SDR50 */
+   {6, 4, 15,  0,},  /* 6: SDR104 */
+   {0},  /* 7: DDR50 */
+   {0},  /* 8: DDR52 */
+   {0},  /* 9: HS200 */
+   },
+   { /* SDIO */
+   {7, 0, 15, 15,},  /* 0: LEGACY 400k */
+   {0},  /* 1: MMC_HS */
+   {6, 0, 15, 15,},  /* 2: SD_HS */
+   {6, 0, 15, 15,},  /* 3: SDR12 */
+   {6, 0,  0,  0,},  /* 4: SDR25 */
+   {4, 0, 12,  0,},  /* 5: SDR50 */
+   {5, 4, 15,  0,},  /* 6: SDR104 */
+   {0},  /* 7: DDR50 */
+   {0},  /* 8: DDR52 */
+   {0},  /* 9: HS200 */
+   }
+};
+
 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 {
int ret;
@@ -66,6 +134,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
if (IS_ERR(priv->reg))
priv->reg = NULL;
 
+   priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
+   if (priv->ctrl_id < 0)
+   priv->ctrl_id = 0;
+
host->priv = priv;
return 0;
 }
@@ -144,7 +216,245 @@ static const struct dw_mci_drv_data hi6220_data = {
.execute_tuning = dw_mci_hi6220_execute_tuning,
 };
 
+static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
+int smpl_phase)
+{
+   u32 drv_phase;
+   u32 smpl_dly;
+   u32 use_smpl_dly = 0;
+   u32 enable_shift = 0;
+   u32 reg_value;
+   int ctrl_id;
+   struct k3_priv *priv;
+
+   priv = host->priv;
+   ctrl_id = priv->ctrl_id;
+
+   drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
+   smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
+   if (smpl_phase == -1)
+   smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
+hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
+
+   switch (timing) {
+   case MMC_TIMING_UHS_SDR104:
+   if (smpl_phase >= USE_DLY_MIN_SMPL &&
+   smpl_phase <= USE_DLY_MAX_SMPL)
+   use_smpl_dly = 1;
+   /* fallthrough */
+   case MMC_TIMING_UHS_SDR50:
+   if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
+

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

答复: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

Re: [PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

[PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

[PATCH v5] mmc: dw_mmc-k3: add sd support for hi3660

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