Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas wrote: > On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote: >> Hi Michal, >> >> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote: >> > Hi Bjorn, >> > >> > On 07/30/2014 01:24 PM, Srikanth Thokala wrote: >> >> Hi Arnd, >> >> >> >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: >> >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: >> Hi Arnd and Rob, >> >> I discussed with Bjorn and we believe this patch is in good shape to >> apply. And Bjorn requires ACKs to apply this patch. So, could you >> guys please review this patch and provided your ACKs to this patch. >> >>> >> >>> Looks great for the most part. I've looked through the whole driver >> >>> again, and I have two small issues remaining: >> >>> >> >>> a) Please clarify in the changeset description why there is no support >> >>>for PCI I/O space. >> >> >> >> Sure, I will add to my changeset. >> >> >> >>> >> >>> b) I think you should use the 'msi-parent' property, and the >> >>>of_pci_find_msi_chip_by_node() to find the msi_chip for the >> >>>PCI controller. This will make it possible to forward MSIs >> >>>to the main interrupt controller in the system, which is more >> >>>efficient. See the pcie-mvebu driver for an example of this. >> >> >> >> Ok, I need to look into this and I will plan to implement on top of this >> >> patch. >> >> >> >>> >> >>> Other than these: >> >>> >> >>> Acked-by: Arnd Bergmann >> >> >> >> Thanks Arnd for the Ack. >> > >> > What's the status on this one? >> >> It looks like Bjorn is on vacation. I have sent v6 patch by adding >> Ack from Arnd, which >> I feel is in good shape to be applied. > > I actually started applying this last night (see [1]), but got some > errors from the build-bot (attached). I haven't looked into them, > but my guess is that you're missing a Kconfig dependency or something > equally minor. These are due to the same config flag name (CONFIG_PCI_XILINX) being used for Microblaze and Zynq platforms. I will fix it and send you next version of patch. Thanks, Srikanth > > Bjorn > > [1] > http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinx=a58f3d0c3b1c4a71a2418c3306fba86c26a49781 > > > -- Forwarded message -- > From: kbuild test robot > To: Bjorn Helgaas > Cc: > Date: Mon, 18 Aug 2014 12:40:06 +0800 > Subject: [pci:pci/host-xilinx] a58f3d0c3b1c4a71a2418c3306fba86c26a49781 BUILD > DONE > git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx > a58f3d0c3b1c4a71a2418c3306fba86c26a49781 PCI: xilinx: Add Xilinx PCIe Host > Bridge IP driver > > drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first > use in this function) > drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to > incomplete type > drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function > 'pci_common_init_dev' [-Werror=implicit-function-declaration] > drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function > 'set_irq_flags' [-Werror=implicit-function-declaration] > drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type > 'struct hw_pci' > drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known > drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified > in initializer > drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified > in initializer > drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' > specified in initializer > drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in > initializer > drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' > specified in initializer > drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in > initializer > drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified > in initializer > drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for > '(anonymous)') > drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct > initializer > drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this > definition or declaration, which is probably not what you want > drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of > 'sys_to_pcie' from incompatible pointer type > drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared > inside parameter list > > elapsed time: 25m > > configs tested: 112 > > pariscc3000_defconfig > parisc b180_defconfig > parisc defconfig > alpha defconfig > pariscallnoconfig > i386 allnoconfig > i386defconfig > i386
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas bhelg...@google.com wrote: On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote: Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote: Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. I actually started applying this last night (see [1]), but got some errors from the build-bot (attached). I haven't looked into them, but my guess is that you're missing a Kconfig dependency or something equally minor. These are due to the same config flag name (CONFIG_PCI_XILINX) being used for Microblaze and Zynq platforms. I will fix it and send you next version of patch. Thanks, Srikanth Bjorn [1] http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinxid=a58f3d0c3b1c4a71a2418c3306fba86c26a49781 -- Forwarded message -- From: kbuild test robot fengguang...@intel.com To: Bjorn Helgaas bhelg...@google.com Cc: Date: Mon, 18 Aug 2014 12:40:06 +0800 Subject: [pci:pci/host-xilinx] a58f3d0c3b1c4a71a2418c3306fba86c26a49781 BUILD DONE git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx a58f3d0c3b1c4a71a2418c3306fba86c26a49781 PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first use in this function) drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to incomplete type drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function 'pci_common_init_dev' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type 'struct hw_pci' drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified in initializer drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified in initializer drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in initializer drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' specified in initializer drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in initializer drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for '(anonymous)') drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct initializer drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this definition or declaration, which is probably not what you want drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of 'sys_to_pcie' from incompatible pointer type drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared inside parameter list elapsed time: 25m configs tested: 112 pariscc3000_defconfig parisc b180_defconfig parisc defconfig alpha defconfig pariscallnoconfig i386 allnoconfig i386defconfig i386 allmodconfig i386 alldefconfig shtitan_defconfig sh
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote: > Hi Michal, > > On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote: > > Hi Bjorn, > > > > On 07/30/2014 01:24 PM, Srikanth Thokala wrote: > >> Hi Arnd, > >> > >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: > >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: > Hi Arnd and Rob, > > I discussed with Bjorn and we believe this patch is in good shape to > apply. And Bjorn requires ACKs to apply this patch. So, could you > guys please review this patch and provided your ACKs to this patch. > >>> > >>> Looks great for the most part. I've looked through the whole driver > >>> again, and I have two small issues remaining: > >>> > >>> a) Please clarify in the changeset description why there is no support > >>>for PCI I/O space. > >> > >> Sure, I will add to my changeset. > >> > >>> > >>> b) I think you should use the 'msi-parent' property, and the > >>>of_pci_find_msi_chip_by_node() to find the msi_chip for the > >>>PCI controller. This will make it possible to forward MSIs > >>>to the main interrupt controller in the system, which is more > >>>efficient. See the pcie-mvebu driver for an example of this. > >> > >> Ok, I need to look into this and I will plan to implement on top of this > >> patch. > >> > >>> > >>> Other than these: > >>> > >>> Acked-by: Arnd Bergmann > >> > >> Thanks Arnd for the Ack. > > > > What's the status on this one? > > It looks like Bjorn is on vacation. I have sent v6 patch by adding > Ack from Arnd, which > I feel is in good shape to be applied. I actually started applying this last night (see [1]), but got some errors from the build-bot (attached). I haven't looked into them, but my guess is that you're missing a Kconfig dependency or something equally minor. Bjorn [1] http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinx=a58f3d0c3b1c4a71a2418c3306fba86c26a49781 --- Begin Message --- git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx a58f3d0c3b1c4a71a2418c3306fba86c26a49781 PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first use in this function) drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to incomplete type drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function 'pci_common_init_dev' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type 'struct hw_pci' drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified in initializer drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified in initializer drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in initializer drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' specified in initializer drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in initializer drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for '(anonymous)') drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct initializer drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this definition or declaration, which is probably not what you want drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of 'sys_to_pcie' from incompatible pointer type drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared inside parameter list elapsed time: 25m configs tested: 112 pariscc3000_defconfig parisc b180_defconfig parisc defconfig alpha defconfig pariscallnoconfig i386 allnoconfig i386defconfig i386 allmodconfig i386 alldefconfig shtitan_defconfig sh rsk7269_defconfig sh sh7785lcr_32bit_defconfig shallnoconfig x86_64 randconfig-c3-0818 x86_64 randconfig-c1-0818 x86_64 randconfig-c0-0818 x86_64 randconfig-c2-0818 ia64 allmodconfig ia64 allnoconfig ia64defconfig ia64
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote: > Hi Bjorn, > > On 07/30/2014 01:24 PM, Srikanth Thokala wrote: >> Hi Arnd, >> >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. >>> >>> Looks great for the most part. I've looked through the whole driver >>> again, and I have two small issues remaining: >>> >>> a) Please clarify in the changeset description why there is no support >>>for PCI I/O space. >> >> Sure, I will add to my changeset. >> >>> >>> b) I think you should use the 'msi-parent' property, and the >>>of_pci_find_msi_chip_by_node() to find the msi_chip for the >>>PCI controller. This will make it possible to forward MSIs >>>to the main interrupt controller in the system, which is more >>>efficient. See the pcie-mvebu driver for an example of this. >> >> Ok, I need to look into this and I will plan to implement on top of this >> patch. >> >>> >>> Other than these: >>> >>> Acked-by: Arnd Bergmann >> >> Thanks Arnd for the Ack. > > What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. > > Srikanth: > Isn't pcie-xilinx.c better name if this is just pcie host bridge? Yes, it looks better. But, many other drivers which are basically drivers for PCIe host controllers has the prefix 'pci-' in the file name. So, I feel it should be fine and would be happy to change if I have to. Thanks Srikanth > > Thanks, > Michal > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ > Maintainer of Linux kernel - Xilinx Zynq ARM architecture > Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform > > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote: Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. Srikanth: Isn't pcie-xilinx.c better name if this is just pcie host bridge? Yes, it looks better. But, many other drivers which are basically drivers for PCIe host controllers has the prefix 'pci-' in the file name. So, I feel it should be fine and would be happy to change if I have to. Thanks Srikanth Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote: Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote: Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. I actually started applying this last night (see [1]), but got some errors from the build-bot (attached). I haven't looked into them, but my guess is that you're missing a Kconfig dependency or something equally minor. Bjorn [1] http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinxid=a58f3d0c3b1c4a71a2418c3306fba86c26a49781 ---BeginMessage--- git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx a58f3d0c3b1c4a71a2418c3306fba86c26a49781 PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first use in this function) drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to incomplete type drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function 'pci_common_init_dev' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type 'struct hw_pci' drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified in initializer drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified in initializer drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in initializer drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' specified in initializer drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in initializer drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for '(anonymous)') drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct initializer drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this definition or declaration, which is probably not what you want drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of 'sys_to_pcie' from incompatible pointer type drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared inside parameter list elapsed time: 25m configs tested: 112 pariscc3000_defconfig parisc b180_defconfig parisc defconfig alpha defconfig pariscallnoconfig i386 allnoconfig i386defconfig i386 allmodconfig i386 alldefconfig shtitan_defconfig sh rsk7269_defconfig sh sh7785lcr_32bit_defconfig shallnoconfig x86_64 randconfig-c3-0818 x86_64 randconfig-c1-0818 x86_64 randconfig-c0-0818 x86_64 randconfig-c2-0818 ia64 allmodconfig ia64 allnoconfig ia64defconfig ia64 alldefconfig x86_64lkp x86_64 rhel powerpc
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: > Hi Arnd, > > On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: >> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: >>> Hi Arnd and Rob, >>> >>> I discussed with Bjorn and we believe this patch is in good shape to >>> apply. And Bjorn requires ACKs to apply this patch. So, could you >>> guys please review this patch and provided your ACKs to this patch. >> >> Looks great for the most part. I've looked through the whole driver >> again, and I have two small issues remaining: >> >> a) Please clarify in the changeset description why there is no support >>for PCI I/O space. > > Sure, I will add to my changeset. > >> >> b) I think you should use the 'msi-parent' property, and the >>of_pci_find_msi_chip_by_node() to find the msi_chip for the >>PCI controller. This will make it possible to forward MSIs >>to the main interrupt controller in the system, which is more >>efficient. See the pcie-mvebu driver for an example of this. > > Ok, I need to look into this and I will plan to implement on top of this > patch. > >> >> Other than these: >> >> Acked-by: Arnd Bergmann > > Thanks Arnd for the Ack. What's the status on this one? Srikanth: Isn't pcie-xilinx.c better name if this is just pcie host bridge? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. What's the status on this one? Srikanth: Isn't pcie-xilinx.c better name if this is just pcie host bridge? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: > On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: >> Hi Arnd and Rob, >> >> I discussed with Bjorn and we believe this patch is in good shape to >> apply. And Bjorn requires ACKs to apply this patch. So, could you >> guys please review this patch and provided your ACKs to this patch. > > Looks great for the most part. I've looked through the whole driver > again, and I have two small issues remaining: > > a) Please clarify in the changeset description why there is no support >for PCI I/O space. Sure, I will add to my changeset. > > b) I think you should use the 'msi-parent' property, and the >of_pci_find_msi_chip_by_node() to find the msi_chip for the >PCI controller. This will make it possible to forward MSIs >to the main interrupt controller in the system, which is more >efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. > > Other than these: > > Acked-by: Arnd Bergmann Thanks Arnd for the Ack. Srikanth > > Arnd > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. Srikanth Arnd -- To unsubscribe from this list: send the line unsubscribe linux-pci in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: > Hi Arnd and Rob, > > I discussed with Bjorn and we believe this patch is in good shape to > apply. And Bjorn requires ACKs to apply this patch. So, could you > guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Other than these: Acked-by: Arnd Bergmann Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> ---
> Changes in v5:
> - Removed unnecessary checking of port structure.
> - Changed the return type of verify_config from int to bool.
> - Renamed following functions,
> xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
> xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
> xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
> - Removed link_up bool flag from port structure, as it is not
> being used.
> - Removed unused constants.
> - Rebased on 3.16-rc6.
> - Fixed some minor comments.
> - Thanks Bjorn for the review.
>
> Changes in v4:
> - Regarding the comments to separate ECAM functionality,
> I have sent a separate patch and it is decided to implement
> it later. The patch is here,
> https://lkml.org/lkml/2014/5/18/54
> - Fixed issue with adding configuration bus resource.
> - Moved the logic for setting up bus resources to probe() from
> pcie_setup().
> - Instead of mapping all the MSI interrupts in the probe, changed
> to map only when a MSI is requested.
> - Earlier, the implementation of legacy and MSI interrupts init-
> is mutually exclusive, now changed to have the legacy interrupts
> init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
> - Regarding the MSI generic implementation comment, I will plan to
> do on top of this driver patch.
> - Rebased on 3.16-rc2.
> - Fixed other minor comments.
> - Thanks Arnd and Bjorn for the review.
>
> Changes in v3:
> - Rebased on v3.15.0-rc1
> - Added support for interrupt-map DT functionality.
> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
> - Modified resource mapping logic as per the series
> "PCI: ARM: add support for generic PCI host controller"
> - Modified devicetree binding documentation to update with interrupt-
> map properties.
> - Use devm calls wherever applicable.
> - Fixed minor comments from Jason
> - Thanks Jason for the review and suggestions.
>
> Changes in v2:
> - Rebased on v3.14.0-rc8
> - Removed IP specific DT properties like include-rc, axibar-num etc.,
> as suggested by Jason and Bjorn, Thanks
> ---
> .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
> drivers/pci/host/Kconfig |7 +
> drivers/pci/host/Makefile |1 +
> drivers/pci/host/pci-xilinx.c | 978
>
> 4 files changed, 1048 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> create mode 100644 drivers/pci/host/pci-xilinx.c
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> new file mode 100644
> index 000..3e2c88d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> @@ -0,0 +1,62 @@
> +* Xilinx AXI PCIe Root Port Bridge DT description
> +
> +Required properties:
> +- #address-cells: Address representation for root ports, set to <3>
> +- #size-cells: Size representation for root ports, set to <2>
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
> +- reg: Should contain AXI PCIe registers location and length
> +- device_type: must be "pci"
> +- interrupts: Should contain AXI PCIe interrupt
> +- interrupt-map-mask,
> + interrupt-map: standard PCI properties to define the mapping of the
> + PCI interface to interrupt numbers.
> +- ranges: ranges for the PCI memory regions (I/O space region is not
> + supported by hardware)
> + Please refer to the standard PCI bus binding document for a more
> + detailed explanation
> +
> +Optional properties:
> +- bus-range: PCI bus numbers covered
> +
> +Interrupt controller child node
>
> +Required properties:
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #address-cells: specifies the number of cells needed to encode an
> + address. The value must be 0.
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +
> +NOTE:
> +The core provides a single interrupt for both INTx/MSI messages. So,
> +created a interrupt controller node to support 'interrupt-map' DT
> +functionality. The driver will create an IRQ domain for this map, decode
> +the four INTx interrupts in ISR and route them to this domain.
> +
> +
> +Example:
> +
> +
> + pci_express: axi-pcie@5000 {
> + #address-cells = <3>;
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Arnd -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
"PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = < 0x5000 0x1000 >;
+ device_type = "pci";
+ interrupts = < 0 52 4 >;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 _intc 1>,
+ <0 0 0 2 _intc 2>,
+ <0 0 0 3 _intc 3>,
+ <0 0 0 4 _intc 4>;
+
[PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4;
+
