Re: [PATCH v5 01/18] arm64: dts: qcom: qcs404: add base dts files
On Fri 09 Nov 01:44 PST 2018, Vinod Koul wrote:
> Add base dts files for QCS404 chipset along with cpu, timer,
> gcc and uart2 nodes.
>
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 175
> +++
> 1 file changed, 175 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> new file mode 100644
> index ..91abcdc78505
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -0,0 +1,175 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, Linaro Limited
> +
> +#include
> +#include
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1920>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU1: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x101>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU2: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x102>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU3: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x103>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + memory@8000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x8000 0 0>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc: soc@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@180 {
> + compatible = "qcom,gcc-qcs404";
> + reg = <0x0180 0x8>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
> + assigned-clock-rates = <1920>;
> + };
> +
> + blsp1_uart2: serial@78b1000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078b1000 0x200>;
> + interrupts = ;
> + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc
> GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "okay";
> + };
> +
> + intc: interrupt-controller@b00 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x0b00 0x1000>,
> + <0x0b002000 0x1000>;
> + };
> +
> + timer@b12 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0b12 0x1000>;
> + clock-frequency = <1920>;
> +
> + frame@b121000 {
> + frame-number = <0>;
> + interrupts = ,
> + ;
> + reg = <0x0b121000 0x1000>,
> + <0x0b122000 0x1000>;
> + };
> +
> + frame@b123000 {
> + frame-number = <1>;
> + interrupts = ;
> + reg = <0x0b123000 0x1000>;
>
[PATCH v5 01/18] arm64: dts: qcom: qcs404: add base dts files
Add base dts files for QCS404 chipset along with cpu, timer,
gcc and uart2 nodes.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++
1 file changed, 175 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
new file mode 100644
index ..91abcdc78505
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, Linaro Limited
+
+#include
+#include
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1920>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x8000 0 0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@180 {
+ compatible = "qcom,gcc-qcs404";
+ reg = <0x0180 0x8>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
+ assigned-clock-rates = <1920>;
+ };
+
+ blsp1_uart2: serial@78b1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b1000 0x200>;
+ interrupts = ;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc
GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "okay";
+ };
+
+ intc: interrupt-controller@b00 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0b00 0x1000>,
+ <0x0b002000 0x1000>;
+ };
+
+ timer@b12 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b12 0x1000>;
+ clock-frequency = <1920>;
+
+ frame@b121000 {
+ frame-number = <0>;
+ interrupts = ,
+;
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = ;
+ reg = <0x0b123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+
