Re: [PATCH v5 05/11] clk: mediatek: add mt6765 clock IDs
Hi Matthias On Tue, 2018-07-17 at 12:24 +0200, Matthias Brugger wrote: > > On 17/07/18 10:52, Mars Cheng wrote: > > Signed-off-by: Mars Cheng > > Signed-off-by: Owen Chen > > Please provide a commit message. > > Thanks, > Matthias Got it, it is my bad, will add it. Thanks. > > > --- > > include/dt-bindings/clock/mt6765-clk.h | 313 > > > > 1 file changed, 313 insertions(+) > > create mode 100644 include/dt-bindings/clock/mt6765-clk.h > > > > diff --git a/include/dt-bindings/clock/mt6765-clk.h > > b/include/dt-bindings/clock/mt6765-clk.h > > new file mode 100644 > > index 000..eb97e56 > > --- /dev/null > > +++ b/include/dt-bindings/clock/mt6765-clk.h > > @@ -0,0 +1,313 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > + > > +#ifndef _DT_BINDINGS_CLK_MT6765_H > > +#define _DT_BINDINGS_CLK_MT6765_H > > + > > +/* FIX Clks */ > > +#define CLK_TOP_CLK26M 0 > > + > > +/* APMIXEDSYS */ > > +#define CLK_APMIXED_ARMPLL_L 0 > > +#define CLK_APMIXED_ARMPLL 1 > > +#define CLK_APMIXED_CCIPLL 2 > > +#define CLK_APMIXED_MAINPLL3 > > +#define CLK_APMIXED_MFGPLL 4 > > +#define CLK_APMIXED_MMPLL 5 > > +#define CLK_APMIXED_UNIV2PLL 6 > > +#define CLK_APMIXED_MSDCPLL7 > > +#define CLK_APMIXED_APLL1 8 > > +#define CLK_APMIXED_MPLL 9 > > +#define CLK_APMIXED_ULPOSC110 > > +#define CLK_APMIXED_ULPOSC211 > > +#define CLK_APMIXED_SSUSB26M 12 > > +#define CLK_APMIXED_APPLL26M 13 > > +#define CLK_APMIXED_MIPIC0_26M 14 > > +#define CLK_APMIXED_MDPLLGP26M 15 > > +#define CLK_APMIXED_MMSYS_F26M 16 > > +#define CLK_APMIXED_UFS26M 17 > > +#define CLK_APMIXED_MIPIC1_26M 18 > > +#define CLK_APMIXED_MEMPLL26M 19 > > +#define CLK_APMIXED_CLKSQ_LVPLL_26M20 > > +#define CLK_APMIXED_MIPID0_26M 21 > > +#define CLK_APMIXED_NR_CLK 22 > > + > > +/* TOPCKGEN */ > > +#define CLK_TOP_SYSPLL 0 > > +#define CLK_TOP_SYSPLL_D2 1 > > +#define CLK_TOP_SYSPLL1_D2 2 > > +#define CLK_TOP_SYSPLL1_D4 3 > > +#define CLK_TOP_SYSPLL1_D8 4 > > +#define CLK_TOP_SYSPLL1_D165 > > +#define CLK_TOP_SYSPLL_D3 6 > > +#define CLK_TOP_SYSPLL2_D2 7 > > +#define CLK_TOP_SYSPLL2_D4 8 > > +#define CLK_TOP_SYSPLL2_D8 9 > > +#define CLK_TOP_SYSPLL_D5 10 > > +#define CLK_TOP_SYSPLL3_D2 11 > > +#define CLK_TOP_SYSPLL3_D4 12 > > +#define CLK_TOP_SYSPLL_D7 13 > > +#define CLK_TOP_SYSPLL4_D2 14 > > +#define CLK_TOP_SYSPLL4_D4 15 > > +#define CLK_TOP_USB20_192M 16 > > +#define CLK_TOP_USB20_192M_D4 17 > > +#define CLK_TOP_USB20_192M_D8 18 > > +#define CLK_TOP_USB20_192M_D16 19 > > +#define CLK_TOP_USB20_192M_D32 20 > > +#define CLK_TOP_UNIVPLL21 > > +#define CLK_TOP_UNIVPLL_D2 22 > > +#define CLK_TOP_UNIVPLL1_D223 > > +#define CLK_TOP_UNIVPLL1_D424 > > +#define CLK_TOP_UNIVPLL_D3 25 > > +#define CLK_TOP_UNIVPLL2_D226 > > +#define CLK_TOP_UNIVPLL2_D427 > > +#define CLK_TOP_UNIVPLL2_D828 > > +#define CLK_TOP_UNIVPLL2_D32 29 > > +#define CLK_TOP_UNIVPLL_D5 30 > > +#define CLK_TOP_UNIVPLL3_D231 > > +#define CLK_TOP_UNIVPLL3_D432 > > +#define CLK_TOP_MMPLL 33 > > +#define CLK_TOP_MMPLL_D2 34 > > +#define CLK_TOP_MPLL 35 > > +#define CLK_TOP_DA_MPLL_104M_DIV 36 > > +#define CLK_TOP_DA_MPLL_52M_DIV37 > > +#define CLK_TOP_MFGPLL 38 > > +#define CLK_TOP_MSDCPLL39 > > +#define CLK_TOP_MSDCPLL_D2 40 > > +#define CLK_TOP_APLL1 41 > > +#define CLK_TOP_APLL1_D2 42 > > +#define CLK_TOP_APLL1_D4 43 > > +#define CLK_TOP_APLL1_D8 44 > > +#define CLK_TOP_ULPOSC145 > > +#define CLK_TOP_ULPOSC1_D2 46 > > +#define CLK_TOP_ULPOSC1_D4 47 > > +#define CLK_TOP_ULPOSC1_D8 48 > > +#define CLK_TOP_ULPOSC1_D1649 > > +#define CLK_TOP_ULPOSC1_D3250 > > +#define CLK_TOP_DMPLL 51 > > +#define CLK_TOP_F_FRTC 52 > > +#define CLK_TOP_F_F26M 53 > > +#define CLK_TOP_AXI54 > > +#define CLK_TOP_MM 55 > > +#define CLK_TOP_SCP56 > > +#define CLK_TOP_MFG57 > > +#define CLK_TOP_F_FUART58 > > +#define CLK_TOP_SPI59 > > +#define CLK_TOP_MSDC50_0 60 > > +#define CLK_TOP_MSDC30_1 6
Re: [PATCH v5 05/11] clk: mediatek: add mt6765 clock IDs
On 17/07/18 10:52, Mars Cheng wrote: > Signed-off-by: Mars Cheng > Signed-off-by: Owen Chen Please provide a commit message. Thanks, Matthias > --- > include/dt-bindings/clock/mt6765-clk.h | 313 > > 1 file changed, 313 insertions(+) > create mode 100644 include/dt-bindings/clock/mt6765-clk.h > > diff --git a/include/dt-bindings/clock/mt6765-clk.h > b/include/dt-bindings/clock/mt6765-clk.h > new file mode 100644 > index 000..eb97e56 > --- /dev/null > +++ b/include/dt-bindings/clock/mt6765-clk.h > @@ -0,0 +1,313 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#ifndef _DT_BINDINGS_CLK_MT6765_H > +#define _DT_BINDINGS_CLK_MT6765_H > + > +/* FIX Clks */ > +#define CLK_TOP_CLK26M 0 > + > +/* APMIXEDSYS */ > +#define CLK_APMIXED_ARMPLL_L 0 > +#define CLK_APMIXED_ARMPLL 1 > +#define CLK_APMIXED_CCIPLL 2 > +#define CLK_APMIXED_MAINPLL 3 > +#define CLK_APMIXED_MFGPLL 4 > +#define CLK_APMIXED_MMPLL5 > +#define CLK_APMIXED_UNIV2PLL 6 > +#define CLK_APMIXED_MSDCPLL 7 > +#define CLK_APMIXED_APLL18 > +#define CLK_APMIXED_MPLL 9 > +#define CLK_APMIXED_ULPOSC1 10 > +#define CLK_APMIXED_ULPOSC2 11 > +#define CLK_APMIXED_SSUSB26M 12 > +#define CLK_APMIXED_APPLL26M 13 > +#define CLK_APMIXED_MIPIC0_26M 14 > +#define CLK_APMIXED_MDPLLGP26M 15 > +#define CLK_APMIXED_MMSYS_F26M 16 > +#define CLK_APMIXED_UFS26M 17 > +#define CLK_APMIXED_MIPIC1_26M 18 > +#define CLK_APMIXED_MEMPLL26M19 > +#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 > +#define CLK_APMIXED_MIPID0_26M 21 > +#define CLK_APMIXED_NR_CLK 22 > + > +/* TOPCKGEN */ > +#define CLK_TOP_SYSPLL 0 > +#define CLK_TOP_SYSPLL_D21 > +#define CLK_TOP_SYSPLL1_D2 2 > +#define CLK_TOP_SYSPLL1_D4 3 > +#define CLK_TOP_SYSPLL1_D8 4 > +#define CLK_TOP_SYSPLL1_D16 5 > +#define CLK_TOP_SYSPLL_D36 > +#define CLK_TOP_SYSPLL2_D2 7 > +#define CLK_TOP_SYSPLL2_D4 8 > +#define CLK_TOP_SYSPLL2_D8 9 > +#define CLK_TOP_SYSPLL_D510 > +#define CLK_TOP_SYSPLL3_D2 11 > +#define CLK_TOP_SYSPLL3_D4 12 > +#define CLK_TOP_SYSPLL_D713 > +#define CLK_TOP_SYSPLL4_D2 14 > +#define CLK_TOP_SYSPLL4_D4 15 > +#define CLK_TOP_USB20_192M 16 > +#define CLK_TOP_USB20_192M_D417 > +#define CLK_TOP_USB20_192M_D818 > +#define CLK_TOP_USB20_192M_D16 19 > +#define CLK_TOP_USB20_192M_D32 20 > +#define CLK_TOP_UNIVPLL 21 > +#define CLK_TOP_UNIVPLL_D2 22 > +#define CLK_TOP_UNIVPLL1_D2 23 > +#define CLK_TOP_UNIVPLL1_D4 24 > +#define CLK_TOP_UNIVPLL_D3 25 > +#define CLK_TOP_UNIVPLL2_D2 26 > +#define CLK_TOP_UNIVPLL2_D4 27 > +#define CLK_TOP_UNIVPLL2_D8 28 > +#define CLK_TOP_UNIVPLL2_D32 29 > +#define CLK_TOP_UNIVPLL_D5 30 > +#define CLK_TOP_UNIVPLL3_D2 31 > +#define CLK_TOP_UNIVPLL3_D4 32 > +#define CLK_TOP_MMPLL33 > +#define CLK_TOP_MMPLL_D2 34 > +#define CLK_TOP_MPLL 35 > +#define CLK_TOP_DA_MPLL_104M_DIV 36 > +#define CLK_TOP_DA_MPLL_52M_DIV 37 > +#define CLK_TOP_MFGPLL 38 > +#define CLK_TOP_MSDCPLL 39 > +#define CLK_TOP_MSDCPLL_D2 40 > +#define CLK_TOP_APLL141 > +#define CLK_TOP_APLL1_D2 42 > +#define CLK_TOP_APLL1_D4 43 > +#define CLK_TOP_APLL1_D8 44 > +#define CLK_TOP_ULPOSC1 45 > +#define CLK_TOP_ULPOSC1_D2 46 > +#define CLK_TOP_ULPOSC1_D4 47 > +#define CLK_TOP_ULPOSC1_D8 48 > +#define CLK_TOP_ULPOSC1_D16 49 > +#define CLK_TOP_ULPOSC1_D32 50 > +#define CLK_TOP_DMPLL51 > +#define CLK_TOP_F_FRTC 52 > +#define CLK_TOP_F_F26M 53 > +#define CLK_TOP_AXI 54 > +#define CLK_TOP_MM 55 > +#define CLK_TOP_SCP 56 > +#define CLK_TOP_MFG 57 > +#define CLK_TOP_F_FUART 58 > +#define CLK_TOP_SPI 59 > +#define CLK_TOP_MSDC50_0 60 > +#define CLK_TOP_MSDC30_1 61 > +#define CLK_TOP_AUDIO62 > +#define CLK_TOP_AUD_163 > +#define CLK_TOP_AUD_ENGEN1 64 > +#define CLK_TOP_F_FDISP_PWM 65 > +#define CLK_TOP_SSPM 66 > +#define CLK_TOP_DXCC 67 > +#define CLK_TOP_I2C 68 > +#define CLK_TOP_F_FPWM 69 > +#define
[PATCH v5 05/11] clk: mediatek: add mt6765 clock IDs
Signed-off-by: Mars Cheng Signed-off-by: Owen Chen --- include/dt-bindings/clock/mt6765-clk.h | 313 1 file changed, 313 insertions(+) create mode 100644 include/dt-bindings/clock/mt6765-clk.h diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h new file mode 100644 index 000..eb97e56 --- /dev/null +++ b/include/dt-bindings/clock/mt6765-clk.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_MT6765_H +#define _DT_BINDINGS_CLK_MT6765_H + +/* FIX Clks */ +#define CLK_TOP_CLK26M 0 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_L 0 +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL3 +#define CLK_APMIXED_MFGPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_UNIV2PLL 6 +#define CLK_APMIXED_MSDCPLL7 +#define CLK_APMIXED_APLL1 8 +#define CLK_APMIXED_MPLL 9 +#define CLK_APMIXED_ULPOSC110 +#define CLK_APMIXED_ULPOSC211 +#define CLK_APMIXED_SSUSB26M 12 +#define CLK_APMIXED_APPLL26M 13 +#define CLK_APMIXED_MIPIC0_26M 14 +#define CLK_APMIXED_MDPLLGP26M 15 +#define CLK_APMIXED_MMSYS_F26M 16 +#define CLK_APMIXED_UFS26M 17 +#define CLK_APMIXED_MIPIC1_26M 18 +#define CLK_APMIXED_MEMPLL26M 19 +#define CLK_APMIXED_CLKSQ_LVPLL_26M20 +#define CLK_APMIXED_MIPID0_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_SYSPLL 0 +#define CLK_TOP_SYSPLL_D2 1 +#define CLK_TOP_SYSPLL1_D2 2 +#define CLK_TOP_SYSPLL1_D4 3 +#define CLK_TOP_SYSPLL1_D8 4 +#define CLK_TOP_SYSPLL1_D165 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL2_D2 7 +#define CLK_TOP_SYSPLL2_D4 8 +#define CLK_TOP_SYSPLL2_D8 9 +#define CLK_TOP_SYSPLL_D5 10 +#define CLK_TOP_SYSPLL3_D2 11 +#define CLK_TOP_SYSPLL3_D4 12 +#define CLK_TOP_SYSPLL_D7 13 +#define CLK_TOP_SYSPLL4_D2 14 +#define CLK_TOP_SYSPLL4_D4 15 +#define CLK_TOP_USB20_192M 16 +#define CLK_TOP_USB20_192M_D4 17 +#define CLK_TOP_USB20_192M_D8 18 +#define CLK_TOP_USB20_192M_D16 19 +#define CLK_TOP_USB20_192M_D32 20 +#define CLK_TOP_UNIVPLL21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D223 +#define CLK_TOP_UNIVPLL1_D424 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D226 +#define CLK_TOP_UNIVPLL2_D427 +#define CLK_TOP_UNIVPLL2_D828 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D231 +#define CLK_TOP_UNIVPLL3_D432 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_MPLL 35 +#define CLK_TOP_DA_MPLL_104M_DIV 36 +#define CLK_TOP_DA_MPLL_52M_DIV37 +#define CLK_TOP_MFGPLL 38 +#define CLK_TOP_MSDCPLL39 +#define CLK_TOP_MSDCPLL_D2 40 +#define CLK_TOP_APLL1 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_ULPOSC145 +#define CLK_TOP_ULPOSC1_D2 46 +#define CLK_TOP_ULPOSC1_D4 47 +#define CLK_TOP_ULPOSC1_D8 48 +#define CLK_TOP_ULPOSC1_D1649 +#define CLK_TOP_ULPOSC1_D3250 +#define CLK_TOP_DMPLL 51 +#define CLK_TOP_F_FRTC 52 +#define CLK_TOP_F_F26M 53 +#define CLK_TOP_AXI54 +#define CLK_TOP_MM 55 +#define CLK_TOP_SCP56 +#define CLK_TOP_MFG57 +#define CLK_TOP_F_FUART58 +#define CLK_TOP_SPI59 +#define CLK_TOP_MSDC50_0 60 +#define CLK_TOP_MSDC30_1 61 +#define CLK_TOP_AUDIO 62 +#define CLK_TOP_AUD_1 63 +#define CLK_TOP_AUD_ENGEN1 64 +#define CLK_TOP_F_FDISP_PWM65 +#define CLK_TOP_SSPM 66 +#define CLK_TOP_DXCC 67 +#define CLK_TOP_I2C68 +#define CLK_TOP_F_FPWM 69 +#define CLK_TOP_F_FSENINF 70 +#define CLK_TOP_AES_FDE71 +#define CLK_TOP_F_BIST2FPC 72 +#define CLK_TOP_ARMPLL_DIVIDER_PLL073 +#define CLK_TOP_ARMPLL_DIVIDER_PLL174 +#define CLK_TOP_ARMPLL_DIVIDER_PLL275 +#define CLK_TOP_DA_USB20_48M_DIV 76 +#define CLK_T
