Re: [PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Heikki Krogerus 
On Wed, Feb 28, 2018 at 04:42:32PM +0100, Hans de Goede wrote:
> Hi,
> 
> On 28-02-18 16:15, Heikki Krogerus wrote:
> > On Wed, Feb 28, 2018 at 04:07:45PM +0100, Hans de Goede wrote:
> > > diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> > > index 96099a245c69..5917e3095e2a 100644
> > > --- a/drivers/usb/host/xhci.h
> > > +++ b/drivers/usb/host/xhci.h
> > > @@ -1825,6 +1825,7 @@ struct xhci_hcd {
> > >   /* Reserved. It was XHCI_U2_DISABLE_WAKE */
> > >   #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
> > >   #define XHCI_HW_LPM_DISABLE (1 << 29)
> > > +#define XHCI_INTEL_USB_ROLE_SW   (1 << 30)
> > 
> > Did you rebased these on tope of the latest usb-next?
> 
> No I did not expect that to be necessary, but I see now that it is.
> I've just done a rebase locally, any other remarks before I send
> out a v6?

Nothing from me.


Thanks,

-- 
heikki

Re: [PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Heikki Krogerus 
On Wed, Feb 28, 2018 at 04:42:32PM +0100, Hans de Goede wrote:
> Hi,
> 
> On 28-02-18 16:15, Heikki Krogerus wrote:
> > On Wed, Feb 28, 2018 at 04:07:45PM +0100, Hans de Goede wrote:
> > > diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> > > index 96099a245c69..5917e3095e2a 100644
> > > --- a/drivers/usb/host/xhci.h
> > > +++ b/drivers/usb/host/xhci.h
> > > @@ -1825,6 +1825,7 @@ struct xhci_hcd {
> > >   /* Reserved. It was XHCI_U2_DISABLE_WAKE */
> > >   #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
> > >   #define XHCI_HW_LPM_DISABLE (1 << 29)
> > > +#define XHCI_INTEL_USB_ROLE_SW   (1 << 30)
> > 
> > Did you rebased these on tope of the latest usb-next?
> 
> No I did not expect that to be necessary, but I see now that it is.
> I've just done a rebase locally, any other remarks before I send
> out a v6?

Nothing from me.


Thanks,

-- 
heikki

Re: [PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Hans de Goede 

Hi,

On 28-02-18 16:15, Heikki Krogerus wrote:

On Wed, Feb 28, 2018 at 04:07:45PM +0100, Hans de Goede wrote:

diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 96099a245c69..5917e3095e2a 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1825,6 +1825,7 @@ struct xhci_hcd {
  /* Reserved. It was XHCI_U2_DISABLE_WAKE */
  #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL   (1 << 28)
  #define XHCI_HW_LPM_DISABLE   (1 << 29)
+#define XHCI_INTEL_USB_ROLE_SW (1 << 30)


Did you rebased these on tope of the latest usb-next?


No I did not expect that to be necessary, but I see now that it is.
I've just done a rebase locally, any other remarks before I send
out a v6?


This does not
apply cleanly on top of linux-next.


Regards,

Hans

Re: [PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Hans de Goede 

Hi,

On 28-02-18 16:15, Heikki Krogerus wrote:

On Wed, Feb 28, 2018 at 04:07:45PM +0100, Hans de Goede wrote:

diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 96099a245c69..5917e3095e2a 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1825,6 +1825,7 @@ struct xhci_hcd {
  /* Reserved. It was XHCI_U2_DISABLE_WAKE */
  #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL   (1 << 28)
  #define XHCI_HW_LPM_DISABLE   (1 << 29)
+#define XHCI_INTEL_USB_ROLE_SW (1 << 30)


Did you rebased these on tope of the latest usb-next?


No I did not expect that to be necessary, but I see now that it is.
I've just done a rebase locally, any other remarks before I send
out a v6?


This does not
apply cleanly on top of linux-next.


Regards,

Hans

Re: [PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Heikki Krogerus 
On Wed, Feb 28, 2018 at 04:07:45PM +0100, Hans de Goede wrote:
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index 96099a245c69..5917e3095e2a 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -1825,6 +1825,7 @@ struct xhci_hcd {
>  /* Reserved. It was XHCI_U2_DISABLE_WAKE */
>  #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL  (1 << 28)
>  #define XHCI_HW_LPM_DISABLE  (1 << 29)
> +#define XHCI_INTEL_USB_ROLE_SW   (1 << 30)

Did you rebased these on tope of the latest usb-next? This does not
apply cleanly on top of linux-next.


Thanks,

-- 
heikki

Re: [PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Heikki Krogerus 
On Wed, Feb 28, 2018 at 04:07:45PM +0100, Hans de Goede wrote:
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index 96099a245c69..5917e3095e2a 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -1825,6 +1825,7 @@ struct xhci_hcd {
>  /* Reserved. It was XHCI_U2_DISABLE_WAKE */
>  #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL  (1 << 28)
>  #define XHCI_HW_LPM_DISABLE  (1 << 29)
> +#define XHCI_INTEL_USB_ROLE_SW   (1 << 30)

Did you rebased these on tope of the latest usb-next? This does not
apply cleanly on top of linux-next.


Thanks,

-- 
heikki

[PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Hans de Goede 
The xHCI controller on various Intel SoCs has an extended cap mmio-range
which contains registers to control the muxing to the xHCI (host mode)
or the dwc3 (device mode) and vbus-detection for the otg usb-phy.

Having a role-sw driver included in the xHCI code (under drivers/usb/host)
is not desirable. So this commit adds a simple handler for this extended
capability, which creates a platform device with the caps mmio region as
resource, this allows us to write a separate platform role-sw driver for
the role-switch.

Note this commit adds a call to the new xhci_ext_cap_init() function
to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must
be called only once. If in the future we also want to handle ext-caps
on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also
be added to other bus probe paths.

Acked-by: Mathias Nyman 
Reviewed-by: Heikki Krogerus 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Hans de Goede 
---
Changes in v4:
-Add Andy's Reviewed-by

Changes in v2:
-Use SPDX license header
-Various small style cleanups / changes
-Add Heikki's Reviewed-by

Changes from some time ago when this patch was part of another patch-set:
-Check xHCI controller PCI device-id instead of only checking for the
 Intel Extended capability ID, as the Extended capability ID is used on
 other model Intel xHCI controllers too
-Add a new generic xhci_ext_cap_init() function and handle the new
 XHCI_INTEL_CHT_USB_MUX quirk there.
-Stop using Cherry Trail / CHT in various places as other Intel SoCs
 (e.g. Broxton / Apollo Lake) also have this
---
 drivers/usb/host/Makefile|  2 +-
 drivers/usb/host/xhci-ext-caps.c | 90 
 drivers/usb/host/xhci-ext-caps.h |  2 +
 drivers/usb/host/xhci-pci.c  |  5 +++
 drivers/usb/host/xhci.h  |  2 +
 5 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/host/xhci-ext-caps.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4ede4ce12366..8a8cffe0b445 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -11,7 +11,7 @@ fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o
 
 fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
 
-xhci-hcd-y := xhci.o xhci-mem.o
+xhci-hcd-y := xhci.o xhci-mem.o xhci-ext-caps.o
 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
 xhci-hcd-y += xhci-trace.o
 
diff --git a/drivers/usb/host/xhci-ext-caps.c b/drivers/usb/host/xhci-ext-caps.c
new file mode 100644
index ..399113f9fc5c
--- /dev/null
+++ b/drivers/usb/host/xhci-ext-caps.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XHCI extended capability handling
+ *
+ * Copyright (c) 2017 Hans de Goede 
+ */
+
+#include 
+#include "xhci.h"
+
+#define USB_SW_DRV_NAME"intel_xhci_usb_sw"
+#define USB_SW_RESOURCE_SIZE   0x400
+
+static void xhci_intel_unregister_pdev(void *arg)
+{
+   platform_device_unregister(arg);
+}
+
+static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 
cap_offset)
+{
+   struct usb_hcd *hcd = xhci_to_hcd(xhci);
+   struct device *dev = hcd->self.controller;
+   struct platform_device *pdev;
+   struct resource res = { 0, };
+   int ret;
+
+   pdev = platform_device_alloc(USB_SW_DRV_NAME, PLATFORM_DEVID_NONE);
+   if (!pdev) {
+   xhci_err(xhci, "couldn't allocate %s platform device\n",
+USB_SW_DRV_NAME);
+   return -ENOMEM;
+   }
+
+   res.start = hcd->rsrc_start + cap_offset;
+   res.end   = res.start + USB_SW_RESOURCE_SIZE - 1;
+   res.name  = USB_SW_DRV_NAME;
+   res.flags = IORESOURCE_MEM;
+
+   ret = platform_device_add_resources(pdev, , 1);
+   if (ret) {
+   dev_err(dev, "couldn't add resources to intel_xhci_usb_sw 
pdev\n");
+   platform_device_put(pdev);
+   return ret;
+   }
+
+   pdev->dev.parent = dev;
+
+   ret = platform_device_add(pdev);
+   if (ret) {
+   dev_err(dev, "couldn't register intel_xhci_usb_sw pdev\n");
+   platform_device_put(pdev);
+   return ret;
+   }
+
+   ret = devm_add_action_or_reset(dev, xhci_intel_unregister_pdev, pdev);
+   if (ret) {
+   dev_err(dev, "couldn't add unregister action for 
intel_xhci_usb_sw pdev\n");
+   return ret;
+   }
+
+   return 0;
+}
+
+int xhci_ext_cap_init(struct xhci_hcd *xhci)
+{
+   void __iomem *base = >cap_regs->hc_capbase;
+   u32 offset, val;
+   int ret;
+
+   offset = xhci_find_next_ext_cap(base, 0, 0);
+
+   while (offset) {
+   val = readl(base + offset);
+
+   switch (XHCI_EXT_CAPS_ID(val)) {
+   case XHCI_EXT_CAPS_VENDOR_INTEL:
+   if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) {
+

[PATCH v5 08/12] xhci: Add Intel extended cap / otg phy mux handling

2018-02-28 Thread Hans de Goede 
The xHCI controller on various Intel SoCs has an extended cap mmio-range
which contains registers to control the muxing to the xHCI (host mode)
or the dwc3 (device mode) and vbus-detection for the otg usb-phy.

Having a role-sw driver included in the xHCI code (under drivers/usb/host)
is not desirable. So this commit adds a simple handler for this extended
capability, which creates a platform device with the caps mmio region as
resource, this allows us to write a separate platform role-sw driver for
the role-switch.

Note this commit adds a call to the new xhci_ext_cap_init() function
to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must
be called only once. If in the future we also want to handle ext-caps
on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also
be added to other bus probe paths.

Acked-by: Mathias Nyman 
Reviewed-by: Heikki Krogerus 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Hans de Goede 
---
Changes in v4:
-Add Andy's Reviewed-by

Changes in v2:
-Use SPDX license header
-Various small style cleanups / changes
-Add Heikki's Reviewed-by

Changes from some time ago when this patch was part of another patch-set:
-Check xHCI controller PCI device-id instead of only checking for the
 Intel Extended capability ID, as the Extended capability ID is used on
 other model Intel xHCI controllers too
-Add a new generic xhci_ext_cap_init() function and handle the new
 XHCI_INTEL_CHT_USB_MUX quirk there.
-Stop using Cherry Trail / CHT in various places as other Intel SoCs
 (e.g. Broxton / Apollo Lake) also have this
---
 drivers/usb/host/Makefile|  2 +-
 drivers/usb/host/xhci-ext-caps.c | 90 
 drivers/usb/host/xhci-ext-caps.h |  2 +
 drivers/usb/host/xhci-pci.c  |  5 +++
 drivers/usb/host/xhci.h  |  2 +
 5 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/host/xhci-ext-caps.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4ede4ce12366..8a8cffe0b445 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -11,7 +11,7 @@ fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o
 
 fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
 
-xhci-hcd-y := xhci.o xhci-mem.o
+xhci-hcd-y := xhci.o xhci-mem.o xhci-ext-caps.o
 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
 xhci-hcd-y += xhci-trace.o
 
diff --git a/drivers/usb/host/xhci-ext-caps.c b/drivers/usb/host/xhci-ext-caps.c
new file mode 100644
index ..399113f9fc5c
--- /dev/null
+++ b/drivers/usb/host/xhci-ext-caps.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XHCI extended capability handling
+ *
+ * Copyright (c) 2017 Hans de Goede 
+ */
+
+#include 
+#include "xhci.h"
+
+#define USB_SW_DRV_NAME"intel_xhci_usb_sw"
+#define USB_SW_RESOURCE_SIZE   0x400
+
+static void xhci_intel_unregister_pdev(void *arg)
+{
+   platform_device_unregister(arg);
+}
+
+static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 
cap_offset)
+{
+   struct usb_hcd *hcd = xhci_to_hcd(xhci);
+   struct device *dev = hcd->self.controller;
+   struct platform_device *pdev;
+   struct resource res = { 0, };
+   int ret;
+
+   pdev = platform_device_alloc(USB_SW_DRV_NAME, PLATFORM_DEVID_NONE);
+   if (!pdev) {
+   xhci_err(xhci, "couldn't allocate %s platform device\n",
+USB_SW_DRV_NAME);
+   return -ENOMEM;
+   }
+
+   res.start = hcd->rsrc_start + cap_offset;
+   res.end   = res.start + USB_SW_RESOURCE_SIZE - 1;
+   res.name  = USB_SW_DRV_NAME;
+   res.flags = IORESOURCE_MEM;
+
+   ret = platform_device_add_resources(pdev, , 1);
+   if (ret) {
+   dev_err(dev, "couldn't add resources to intel_xhci_usb_sw 
pdev\n");
+   platform_device_put(pdev);
+   return ret;
+   }
+
+   pdev->dev.parent = dev;
+
+   ret = platform_device_add(pdev);
+   if (ret) {
+   dev_err(dev, "couldn't register intel_xhci_usb_sw pdev\n");
+   platform_device_put(pdev);
+   return ret;
+   }
+
+   ret = devm_add_action_or_reset(dev, xhci_intel_unregister_pdev, pdev);
+   if (ret) {
+   dev_err(dev, "couldn't add unregister action for 
intel_xhci_usb_sw pdev\n");
+   return ret;
+   }
+
+   return 0;
+}
+
+int xhci_ext_cap_init(struct xhci_hcd *xhci)
+{
+   void __iomem *base = >cap_regs->hc_capbase;
+   u32 offset, val;
+   int ret;
+
+   offset = xhci_find_next_ext_cap(base, 0, 0);
+
+   while (offset) {
+   val = readl(base + offset);
+
+   switch (XHCI_EXT_CAPS_ID(val)) {
+   case XHCI_EXT_CAPS_VENDOR_INTEL:
+   if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) {
+   ret = xhci_create_intel_xhci_sw_pdev(xhci,
+