Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Vivek, On Mon, Jan 14, 2013 at 12:06 AM, Vivek Gautam wrote: >> Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it. >> Can we just do like this .. >> #define HOST_CTRL0_FSEL_MASK (0x7 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 << 16) >> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << 16) I don't have a problem with just putting the << 16 there... > Actually missed one thing here, this "HOST_CTRL0_FSEL_CLKSEL_XX" is > being used by > HOST/OTG blocks to prepare reference clock, that's the reason we kept > #define HOST_CTRL0_FSEL(_x) ((_x) << 16) > and #define OTG_SYS_FSEL(_x) ((_x) << 4) > where (_x) is the reference clock returned from > samsung_usbphy_get_refclk_freq(). I feel like samsung_usbphy_get_refclk_freq() is supposed to be returning an already shifted value. ...at least that's how it appears to work with existing code. Why does it feel like that? ...because with existing code we have: #define PHYCLK_CLKSEL_MASK (0x3 << 0) #define PHYCLK_CLKSEL_48M (0x0 << 0) #define PHYCLK_CLKSEL_12M (0x2 << 0) #define PHYCLK_CLKSEL_24M (0x3 << 0) Those #defines are what are returned by samsung_usbphy_get_refclk_freq(). The fact that the "<< 0" is there implies (to me) that the existing function would return shifted values if it were applicable. For exynos you are having the same function return things like: #define FSEL_CLKSEL_50M (0x7) #define FSEL_CLKSEL_24M (0x5) #define FSEL_CLKSEL_20M (0x4) ...to me that means that the exynos code is returning unshifted values. If you say that samsung_usbphy_get_refclk_freq() is in charge of returning shifted values then you no longer need the HOST_CTRL0_FSEL() macro. In any case, I will defer to whatever Felipe thinks is best here (if he has an opinion on it). I am only pointing out that the exynos code and existing code seem to be specifying things differently. That's weird to me. > so we can change this to something like > >case 10 * MHZ: > refclk_freq = FSEL_CLKSEL_10M; > break; > and so on. > will this be fine ? Seems good to me. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug,
On Mon, Jan 14, 2013 at 11:15 AM, Vivek Gautam
wrote:
> Hi Doug,
>
>
> On Sat, Jan 12, 2013 at 6:20 AM, Doug Anderson wrote:
>> Vivek,
>>
>> On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam
>> wrote:
> +#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
> +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
> +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
> +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
> +
> +#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
> +#define HOST_CTRL0_FSEL(_x)((_x) << 16)
> +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
> +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
> +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
> +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
> +#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
> +#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
> +#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
makes it match the older phy more closely.
>>> Wouldn't it hamper the readability when shifts are used ??
>>> I mean if we have something like this -
>>>
>>> phyhost |= HOST_CTRL0_FSEL(phyclk)
>>>
>>> so, if we are using the shifts then
>>> phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M << HOST_CTRL0_FSEL_SHIFT)
>>
>> I was actually suggesting modifying the #defines like this:
>>
>> #define HOST_CTRL0_FSEL_SHIFT 16
>> #define HOST_CTRL0_FSEL_MASK (0x7 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << HOST_CTRL0_FSEL_SHIFT)
>>
>> ...then the code doesn't need to think about shifts, right?
>>
>
> right right, sorry i din't get your point earlier. :-(
>
> this way things will be similar in samsung_usbphy_get_refclk_freq()
> across exynos 5 and older SoCs.
>
> Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it.
> Can we just do like this ..
> #define HOST_CTRL0_FSEL_MASK (0x7 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << 16)
>
Actually missed one thing here, this "HOST_CTRL0_FSEL_CLKSEL_XX" is
being used by
HOST/OTG blocks to prepare reference clock, that's the reason we kept
#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
and #define OTG_SYS_FSEL(_x) ((_x) << 4)
where (_x) is the reference clock returned from
samsung_usbphy_get_refclk_freq().
So in order to avoid confusion we can change the macro names only and
keep something like
#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
#define FSEL_CLKSEL_50M (0x7)
#define FSEL_CLKSEL_24M (0x5)
#define FSEL_CLKSEL_20M (0x4)
#define FSEL_CLKSEL_19200K (0x3)
#define FSEL_CLKSEL_12M (0x2)
#define FSEL_CLKSEL_10M (0x1)
#define FSEL_CLKSEL_9600K(0x0)
...
#define OTG_SYS_FSEL_MASK (0x7 << 4)
#define OTG_SYS_FSEL(_x) ((_x) << 4)
>>
> if (IS_ERR(ref_clk)) {
> dev_err(sphy->dev, "Failed to get reference clock\n");
> return PTR_ERR(ref_clk);
> }
>
> - switch (clk_get_rate(ref_clk)) {
> - case 12 * MHZ:
> - refclk_freq = PHYCLK_CLKSEL_12M;
> - break;
> - case 24 * MHZ:
> - refclk_freq = PHYCLK_CLKSEL_24M;
> - break;
> - case 48 * MHZ:
> - refclk_freq = PHYCLK_CLKSEL_48M;
> - break;
> - default:
> - if (sphy->cpu_type == TYPE_S3C64XX)
> - refclk_freq = PHYCLK_CLKSEL_48M;
> - else
> + if (sphy->cpu_type == TYPE_EXYNOS5250) {
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug,
On Mon, Jan 14, 2013 at 11:15 AM, Vivek Gautam
gautamvivek1...@gmail.com wrote:
Hi Doug,
On Sat, Jan 12, 2013 at 6:20 AM, Doug Anderson diand...@chromium.org wrote:
Vivek,
On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam gautamvivek1...@gmail.com
wrote:
+#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
+#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19)
+#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 19)
+#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 19)
+
+#define HOST_CTRL0_FSEL_MASK (0x7 16)
+#define HOST_CTRL0_FSEL(_x)((_x) 16)
+#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
+#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
+#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
+#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
+#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
+#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
+#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
makes it match the older phy more closely.
Wouldn't it hamper the readability when shifts are used ??
I mean if we have something like this -
phyhost |= HOST_CTRL0_FSEL(phyclk)
so, if we are using the shifts then
phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M HOST_CTRL0_FSEL_SHIFT)
I was actually suggesting modifying the #defines like this:
#define HOST_CTRL0_FSEL_SHIFT 16
#define HOST_CTRL0_FSEL_MASK (0x7 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 HOST_CTRL0_FSEL_SHIFT)
...then the code doesn't need to think about shifts, right?
right right, sorry i din't get your point earlier. :-(
this way things will be similar in samsung_usbphy_get_refclk_freq()
across exynos 5 and older SoCs.
Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it.
Can we just do like this ..
#define HOST_CTRL0_FSEL_MASK (0x7 16)
#define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 16)
#define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 16)
#define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 16)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 16)
#define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 16)
#define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 16)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 16)
Actually missed one thing here, this HOST_CTRL0_FSEL_CLKSEL_XX is
being used by
HOST/OTG blocks to prepare reference clock, that's the reason we kept
#define HOST_CTRL0_FSEL(_x) ((_x) 16)
and #define OTG_SYS_FSEL(_x) ((_x) 4)
where (_x) is the reference clock returned from
samsung_usbphy_get_refclk_freq().
So in order to avoid confusion we can change the macro names only and
keep something like
#define HOST_CTRL0_FSEL_MASK (0x7 16)
#define HOST_CTRL0_FSEL(_x) ((_x) 16)
#define FSEL_CLKSEL_50M (0x7)
#define FSEL_CLKSEL_24M (0x5)
#define FSEL_CLKSEL_20M (0x4)
#define FSEL_CLKSEL_19200K (0x3)
#define FSEL_CLKSEL_12M (0x2)
#define FSEL_CLKSEL_10M (0x1)
#define FSEL_CLKSEL_9600K(0x0)
...
#define OTG_SYS_FSEL_MASK (0x7 4)
#define OTG_SYS_FSEL(_x) ((_x) 4)
if (IS_ERR(ref_clk)) {
dev_err(sphy-dev, Failed to get reference clock\n);
return PTR_ERR(ref_clk);
}
- switch (clk_get_rate(ref_clk)) {
- case 12 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_12M;
- break;
- case 24 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_24M;
- break;
- case 48 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_48M;
- break;
- default:
- if (sphy-cpu_type == TYPE_S3C64XX)
- refclk_freq = PHYCLK_CLKSEL_48M;
- else
+ if (sphy-cpu_type == TYPE_EXYNOS5250) {
+ /* set clock frequency for PLL */
+ switch (clk_get_rate(ref_clk)) {
+ case 96 * 10:
nit: change to 9600 * KHZ to match; below too.
sure.
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_9600K;
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Vivek, On Mon, Jan 14, 2013 at 12:06 AM, Vivek Gautam gautamvivek1...@gmail.com wrote: Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it. Can we just do like this .. #define HOST_CTRL0_FSEL_MASK (0x7 16) #define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 16) #define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 16) #define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 16) #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 16) #define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 16) #define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 16) #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 16) I don't have a problem with just putting the 16 there... Actually missed one thing here, this HOST_CTRL0_FSEL_CLKSEL_XX is being used by HOST/OTG blocks to prepare reference clock, that's the reason we kept #define HOST_CTRL0_FSEL(_x) ((_x) 16) and #define OTG_SYS_FSEL(_x) ((_x) 4) where (_x) is the reference clock returned from samsung_usbphy_get_refclk_freq(). I feel like samsung_usbphy_get_refclk_freq() is supposed to be returning an already shifted value. ...at least that's how it appears to work with existing code. Why does it feel like that? ...because with existing code we have: #define PHYCLK_CLKSEL_MASK (0x3 0) #define PHYCLK_CLKSEL_48M (0x0 0) #define PHYCLK_CLKSEL_12M (0x2 0) #define PHYCLK_CLKSEL_24M (0x3 0) Those #defines are what are returned by samsung_usbphy_get_refclk_freq(). The fact that the 0 is there implies (to me) that the existing function would return shifted values if it were applicable. For exynos you are having the same function return things like: #define FSEL_CLKSEL_50M (0x7) #define FSEL_CLKSEL_24M (0x5) #define FSEL_CLKSEL_20M (0x4) ...to me that means that the exynos code is returning unshifted values. If you say that samsung_usbphy_get_refclk_freq() is in charge of returning shifted values then you no longer need the HOST_CTRL0_FSEL() macro. In any case, I will defer to whatever Felipe thinks is best here (if he has an opinion on it). I am only pointing out that the exynos code and existing code seem to be specifying things differently. That's weird to me. so we can change this to something like case 10 * MHZ: refclk_freq = FSEL_CLKSEL_10M; break; and so on. will this be fine ? Seems good to me. -Doug -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug,
On Sat, Jan 12, 2013 at 6:20 AM, Doug Anderson wrote:
> Vivek,
>
> On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam
> wrote:
+#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
+#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
+#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
+#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
+
+#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
+#define HOST_CTRL0_FSEL(_x)((_x) << 16)
+#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
+#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
+#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
+#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
+#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
+#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
+#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
>>>
>>> Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
>>> makes it match the older phy more closely.
>>>
>> Wouldn't it hamper the readability when shifts are used ??
>> I mean if we have something like this -
>>
>> phyhost |= HOST_CTRL0_FSEL(phyclk)
>>
>> so, if we are using the shifts then
>> phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M << HOST_CTRL0_FSEL_SHIFT)
>
> I was actually suggesting modifying the #defines like this:
>
> #define HOST_CTRL0_FSEL_SHIFT 16
> #define HOST_CTRL0_FSEL_MASK (0x7 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << HOST_CTRL0_FSEL_SHIFT)
>
> ...then the code doesn't need to think about shifts, right?
>
right right, sorry i din't get your point earlier. :-(
this way things will be similar in samsung_usbphy_get_refclk_freq()
across exynos 5 and older SoCs.
Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it.
Can we just do like this ..
#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << 16)
>
if (IS_ERR(ref_clk)) {
dev_err(sphy->dev, "Failed to get reference clock\n");
return PTR_ERR(ref_clk);
}
- switch (clk_get_rate(ref_clk)) {
- case 12 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_12M;
- break;
- case 24 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_24M;
- break;
- case 48 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_48M;
- break;
- default:
- if (sphy->cpu_type == TYPE_S3C64XX)
- refclk_freq = PHYCLK_CLKSEL_48M;
- else
+ if (sphy->cpu_type == TYPE_EXYNOS5250) {
+ /* set clock frequency for PLL */
+ switch (clk_get_rate(ref_clk)) {
+ case 96 * 10:
>>>
>>> nit: change to 9600 * KHZ to match; below too.
>>>
>> sure.
>>
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_9600K;
>>>
>>> Why |= with 0?
>>>
>> kept this just to keep things look similar :-). will remove this line,
>
> My comment was about keeping things similar. Right now the 5250 code
> has the |= and the non-5250 code doesn't. I don't care which is
> picked but the two sides of the "if" should be symmetric.
>
True, it's good to maintain symmetry in the code.
I shall amend the code as suggested.
> See parts of the patch below.
>
+ break;
+ case 10 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_10M;
+ break;
+ case 12 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_12M;
+ break;
+ case 192 * 10:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_19200K;
+ break;
+ case 20 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_20M;
+ break;
+
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug,
On Sat, Jan 12, 2013 at 6:20 AM, Doug Anderson diand...@chromium.org wrote:
Vivek,
On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam gautamvivek1...@gmail.com
wrote:
+#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
+#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19)
+#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 19)
+#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 19)
+
+#define HOST_CTRL0_FSEL_MASK (0x7 16)
+#define HOST_CTRL0_FSEL(_x)((_x) 16)
+#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
+#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
+#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
+#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
+#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
+#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
+#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
makes it match the older phy more closely.
Wouldn't it hamper the readability when shifts are used ??
I mean if we have something like this -
phyhost |= HOST_CTRL0_FSEL(phyclk)
so, if we are using the shifts then
phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M HOST_CTRL0_FSEL_SHIFT)
I was actually suggesting modifying the #defines like this:
#define HOST_CTRL0_FSEL_SHIFT 16
#define HOST_CTRL0_FSEL_MASK (0x7 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 HOST_CTRL0_FSEL_SHIFT)
...then the code doesn't need to think about shifts, right?
right right, sorry i din't get your point earlier. :-(
this way things will be similar in samsung_usbphy_get_refclk_freq()
across exynos 5 and older SoCs.
Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it.
Can we just do like this ..
#define HOST_CTRL0_FSEL_MASK (0x7 16)
#define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 16)
#define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 16)
#define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 16)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 16)
#define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 16)
#define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 16)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 16)
if (IS_ERR(ref_clk)) {
dev_err(sphy-dev, Failed to get reference clock\n);
return PTR_ERR(ref_clk);
}
- switch (clk_get_rate(ref_clk)) {
- case 12 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_12M;
- break;
- case 24 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_24M;
- break;
- case 48 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_48M;
- break;
- default:
- if (sphy-cpu_type == TYPE_S3C64XX)
- refclk_freq = PHYCLK_CLKSEL_48M;
- else
+ if (sphy-cpu_type == TYPE_EXYNOS5250) {
+ /* set clock frequency for PLL */
+ switch (clk_get_rate(ref_clk)) {
+ case 96 * 10:
nit: change to 9600 * KHZ to match; below too.
sure.
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_9600K;
Why |= with 0?
kept this just to keep things look similar :-). will remove this line,
My comment was about keeping things similar. Right now the 5250 code
has the |= and the non-5250 code doesn't. I don't care which is
picked but the two sides of the if should be symmetric.
True, it's good to maintain symmetry in the code.
I shall amend the code as suggested.
See parts of the patch below.
+ break;
+ case 10 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_10M;
+ break;
+ case 12 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_12M;
+ break;
+ case 192 * 10:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_19200K;
+ break;
+ case 20 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_20M;
+ break;
+ case 50 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_50M;
+ break;
+ case 24 * MHZ:
+ default:
+ /* default reference clock */
+ refclk_freq |=
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Vivek,
On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam wrote:
>>> +#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
>>> +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
>>> +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
>>> +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
>>> +
>>> +#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
>>> +#define HOST_CTRL0_FSEL(_x)((_x) << 16)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
>>> +#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
>>
>> Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
>> makes it match the older phy more closely.
>>
> Wouldn't it hamper the readability when shifts are used ??
> I mean if we have something like this -
>
> phyhost |= HOST_CTRL0_FSEL(phyclk)
>
> so, if we are using the shifts then
> phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M << HOST_CTRL0_FSEL_SHIFT)
I was actually suggesting modifying the #defines like this:
#define HOST_CTRL0_FSEL_SHIFT 16
#define HOST_CTRL0_FSEL_MASK (0x7 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 << HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << HOST_CTRL0_FSEL_SHIFT)
...then the code doesn't need to think about shifts, right?
>>> if (IS_ERR(ref_clk)) {
>>> dev_err(sphy->dev, "Failed to get reference clock\n");
>>> return PTR_ERR(ref_clk);
>>> }
>>>
>>> - switch (clk_get_rate(ref_clk)) {
>>> - case 12 * MHZ:
>>> - refclk_freq = PHYCLK_CLKSEL_12M;
>>> - break;
>>> - case 24 * MHZ:
>>> - refclk_freq = PHYCLK_CLKSEL_24M;
>>> - break;
>>> - case 48 * MHZ:
>>> - refclk_freq = PHYCLK_CLKSEL_48M;
>>> - break;
>>> - default:
>>> - if (sphy->cpu_type == TYPE_S3C64XX)
>>> - refclk_freq = PHYCLK_CLKSEL_48M;
>>> - else
>>> + if (sphy->cpu_type == TYPE_EXYNOS5250) {
>>> + /* set clock frequency for PLL */
>>> + switch (clk_get_rate(ref_clk)) {
>>> + case 96 * 10:
>>
>> nit: change to 9600 * KHZ to match; below too.
>>
> sure.
>
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_9600K;
>>
>> Why |= with 0?
>>
> kept this just to keep things look similar :-). will remove this line,
My comment was about keeping things similar. Right now the 5250 code
has the |= and the non-5250 code doesn't. I don't care which is
picked but the two sides of the "if" should be symmetric.
See parts of the patch below.
>>> + break;
>>> + case 10 * MHZ:
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_10M;
>>> + break;
>>> + case 12 * MHZ:
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_12M;
>>> + break;
>>> + case 192 * 10:
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_19200K;
>>> + break;
>>> + case 20 * MHZ:
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_20M;
>>> + break;
>>> + case 50 * MHZ:
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_50M;
>>> + break;
>>> + case 24 * MHZ:
>>> + default:
>>> + /* default reference clock */
>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_24M;
>>> + break;
>>> + }
>>> + } else {
>>> + switch (clk_get_rate(ref_clk)) {
>>> + case 12 * MHZ:
>>> + refclk_freq = PHYCLK_CLKSEL_12M;
>>> + break;
>>> + case 24 * MHZ:
>>> refclk_freq = PHYCLK_CLKSEL_24M;
>>> - break;
>>> + break;
>>> + case 48 * MHZ:
>>> + refclk_freq = PHYCLK_CLKSEL_48M;
>>> + break;
>>> + default:
>>> + if (sphy->cpu_type == TYPE_S3C64XX)
>>> +
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Felipe, On Fri, Jan 11, 2013 at 6:28 PM, Felipe Balbi wrote: > Hi, > > On Fri, Jan 11, 2013 at 06:10:48PM +0530, Vivek Gautam wrote: >> Hi Doug, >> >> Sorry!! for the delayed response. >> >> >> On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson wrote: >> > Vivek, >> > >> > I don't really have a good 1 foot view about how all of the USB >> > bits fit together, but a few detail-oriented comments below. >> > >> > >> > On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam >> > wrote: >> >> This patch adds host phy support to samsung-usbphy.c and >> >> further adds support for samsung's exynos5250 usb-phy. >> >> >> >> Signed-off-by: Praveen Paneri >> >> Signed-off-by: Vivek Gautam >> >> --- >> >> .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- >> >> drivers/usb/phy/Kconfig|2 +- >> >> drivers/usb/phy/samsung-usbphy.c | 465 >> >> ++-- >> >> include/linux/usb/samsung_usb_phy.h| 13 + >> >> 4 files changed, 454 insertions(+), 51 deletions(-) >> >> >> >> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> index a7b28b2..2ec5400 100644 >> >> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> @@ -1,23 +1,38 @@ >> >> * Samsung's usb phy transceiver >> >> >> >> -The Samsung's phy transceiver is used for controlling usb otg phy for >> >> -s3c-hsotg usb device controller. >> >> +The Samsung's phy transceiver is used for controlling usb phy for >> >> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers >> >> +across Samsung SOCs. >> >> TODO: Adding the PHY binding with controller(s) according to the under >> >> developement generic PHY driver. >> >> >> >> Required properties: >> >> + >> >> +Exynos4210: >> >> - compatible : should be "samsung,exynos4210-usbphy" >> >> - reg : base physical address of the phy registers and length of memory >> >> mapped >> >> region. >> >> >> >> +Exynos5250: >> >> +- compatible : should be "samsung,exynos5250-usbphy" >> >> +- reg : base physical address of the phy registers and length of memory >> >> mapped >> >> + region. >> >> + >> >> Optional properties: >> >> - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which >> >> provides >> >> binding data to enable/disable device PHY handled >> >> by >> >> - PMU register. >> >> + PMU register; or to configure usb2.0 phy handled >> >> by >> >> + SYSREG. >> >> >> >> Required properties: >> >> - compatible : should be "samsung,usbdev-phyctrl" >> >> for >> >> - DEVICE type phy. >> >> + DEVICE type phy; or >> >> + should be >> >> "samsung,usbhost-phyctrl" for >> >> + HOST type phy; or >> >> + should be "samsung,usb-phycfg" for >> >> + USB2.0 PHY_CFG. >> >> - samsung,phyhandle-reg: base physical address of >> >> - PHY_CONTROL register in >> >> PMU. >> >> +PHY_CONTROL register in >> >> PMU; >> >> +or USB2.0 PHY_CFG >> >> register >> >> +in SYSREG. >> >> - samsung,enable-mask : should be '1' >> >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig >> >> index 17ad743..13c0eaf 100644 >> >> --- a/drivers/usb/phy/Kconfig >> >> +++ b/drivers/usb/phy/Kconfig >> >> @@ -47,7 +47,7 @@ config USB_RCAR_PHY >> >> >> >> config SAMSUNG_USBPHY >> >> bool "Samsung USB PHY controller Driver" >> >> - depends on USB_S3C_HSOTG >> >> + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS >> >> select USB_OTG_UTILS >> >> help >> >> Enable this to support Samsung USB phy controller for samsung >> >> diff --git a/drivers/usb/phy/samsung-usbphy.c >> >> b/drivers/usb/phy/samsung-usbphy.c >> >> index 4ceabe3..621348a 100644 >> >> --- a/drivers/usb/phy/samsung-usbphy.c >> >> +++ b/drivers/usb/phy/samsung-usbphy.c >> >> @@ -5,7 +5,8 @@ >> >> * >> >> * Author: Praveen Paneri >> >> * >> >> - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG >> >> controller >> >> + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P >> >> and >> >> + * OHCI-EXYNOS controllers. >> >> * >> >> * This program is free software; you can redistribute it and/or modify >> >> * it under the terms of the GNU General Public License version 2 as >> >> @@ -24,7 +25,7 @@ >> >> #include >> >>
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi, On Fri, Jan 11, 2013 at 06:10:48PM +0530, Vivek Gautam wrote: > Hi Doug, > > Sorry!! for the delayed response. > > > On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson wrote: > > Vivek, > > > > I don't really have a good 1 foot view about how all of the USB > > bits fit together, but a few detail-oriented comments below. > > > > > > On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam > > wrote: > >> This patch adds host phy support to samsung-usbphy.c and > >> further adds support for samsung's exynos5250 usb-phy. > >> > >> Signed-off-by: Praveen Paneri > >> Signed-off-by: Vivek Gautam > >> --- > >> .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- > >> drivers/usb/phy/Kconfig|2 +- > >> drivers/usb/phy/samsung-usbphy.c | 465 > >> ++-- > >> include/linux/usb/samsung_usb_phy.h| 13 + > >> 4 files changed, 454 insertions(+), 51 deletions(-) > >> > >> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > >> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > >> index a7b28b2..2ec5400 100644 > >> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > >> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > >> @@ -1,23 +1,38 @@ > >> * Samsung's usb phy transceiver > >> > >> -The Samsung's phy transceiver is used for controlling usb otg phy for > >> -s3c-hsotg usb device controller. > >> +The Samsung's phy transceiver is used for controlling usb phy for > >> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers > >> +across Samsung SOCs. > >> TODO: Adding the PHY binding with controller(s) according to the under > >> developement generic PHY driver. > >> > >> Required properties: > >> + > >> +Exynos4210: > >> - compatible : should be "samsung,exynos4210-usbphy" > >> - reg : base physical address of the phy registers and length of memory > >> mapped > >> region. > >> > >> +Exynos5250: > >> +- compatible : should be "samsung,exynos5250-usbphy" > >> +- reg : base physical address of the phy registers and length of memory > >> mapped > >> + region. > >> + > >> Optional properties: > >> - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which > >> provides > >> binding data to enable/disable device PHY handled > >> by > >> - PMU register. > >> + PMU register; or to configure usb2.0 phy handled by > >> + SYSREG. > >> > >> Required properties: > >> - compatible : should be "samsung,usbdev-phyctrl" > >> for > >> - DEVICE type phy. > >> + DEVICE type phy; or > >> + should be "samsung,usbhost-phyctrl" > >> for > >> + HOST type phy; or > >> + should be "samsung,usb-phycfg" for > >> + USB2.0 PHY_CFG. > >> - samsung,phyhandle-reg: base physical address of > >> - PHY_CONTROL register in > >> PMU. > >> +PHY_CONTROL register in > >> PMU; > >> +or USB2.0 PHY_CFG register > >> +in SYSREG. > >> - samsung,enable-mask : should be '1' > >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig > >> index 17ad743..13c0eaf 100644 > >> --- a/drivers/usb/phy/Kconfig > >> +++ b/drivers/usb/phy/Kconfig > >> @@ -47,7 +47,7 @@ config USB_RCAR_PHY > >> > >> config SAMSUNG_USBPHY > >> bool "Samsung USB PHY controller Driver" > >> - depends on USB_S3C_HSOTG > >> + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS > >> select USB_OTG_UTILS > >> help > >> Enable this to support Samsung USB phy controller for samsung > >> diff --git a/drivers/usb/phy/samsung-usbphy.c > >> b/drivers/usb/phy/samsung-usbphy.c > >> index 4ceabe3..621348a 100644 > >> --- a/drivers/usb/phy/samsung-usbphy.c > >> +++ b/drivers/usb/phy/samsung-usbphy.c > >> @@ -5,7 +5,8 @@ > >> * > >> * Author: Praveen Paneri > >> * > >> - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG > >> controller > >> + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P > >> and > >> + * OHCI-EXYNOS controllers. > >> * > >> * This program is free software; you can redistribute it and/or modify > >> * it under the terms of the GNU General Public License version 2 as > >> @@ -24,7 +25,7 @@ > >> #include > >> #include > >> #include > >> -#include > >> +#include > >> #include > >> > >> /* Register definitions */ > >> @@ -56,6 +57,103 @@ > >> #define RSTCON_HLINK_SWRST (0x1 << 1) > >>
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug, Sorry!! for the delayed response. On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson wrote: > Vivek, > > I don't really have a good 1 foot view about how all of the USB > bits fit together, but a few detail-oriented comments below. > > > On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam > wrote: >> This patch adds host phy support to samsung-usbphy.c and >> further adds support for samsung's exynos5250 usb-phy. >> >> Signed-off-by: Praveen Paneri >> Signed-off-by: Vivek Gautam >> --- >> .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- >> drivers/usb/phy/Kconfig|2 +- >> drivers/usb/phy/samsung-usbphy.c | 465 >> ++-- >> include/linux/usb/samsung_usb_phy.h| 13 + >> 4 files changed, 454 insertions(+), 51 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> index a7b28b2..2ec5400 100644 >> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> @@ -1,23 +1,38 @@ >> * Samsung's usb phy transceiver >> >> -The Samsung's phy transceiver is used for controlling usb otg phy for >> -s3c-hsotg usb device controller. >> +The Samsung's phy transceiver is used for controlling usb phy for >> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers >> +across Samsung SOCs. >> TODO: Adding the PHY binding with controller(s) according to the under >> developement generic PHY driver. >> >> Required properties: >> + >> +Exynos4210: >> - compatible : should be "samsung,exynos4210-usbphy" >> - reg : base physical address of the phy registers and length of memory >> mapped >> region. >> >> +Exynos5250: >> +- compatible : should be "samsung,exynos5250-usbphy" >> +- reg : base physical address of the phy registers and length of memory >> mapped >> + region. >> + >> Optional properties: >> - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which >> provides >> binding data to enable/disable device PHY handled by >> - PMU register. >> + PMU register; or to configure usb2.0 phy handled by >> + SYSREG. >> >> Required properties: >> - compatible : should be "samsung,usbdev-phyctrl" for >> - DEVICE type phy. >> + DEVICE type phy; or >> + should be "samsung,usbhost-phyctrl" >> for >> + HOST type phy; or >> + should be "samsung,usb-phycfg" for >> + USB2.0 PHY_CFG. >> - samsung,phyhandle-reg: base physical address of >> - PHY_CONTROL register in PMU. >> +PHY_CONTROL register in PMU; >> +or USB2.0 PHY_CFG register >> +in SYSREG. >> - samsung,enable-mask : should be '1' >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig >> index 17ad743..13c0eaf 100644 >> --- a/drivers/usb/phy/Kconfig >> +++ b/drivers/usb/phy/Kconfig >> @@ -47,7 +47,7 @@ config USB_RCAR_PHY >> >> config SAMSUNG_USBPHY >> bool "Samsung USB PHY controller Driver" >> - depends on USB_S3C_HSOTG >> + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS >> select USB_OTG_UTILS >> help >> Enable this to support Samsung USB phy controller for samsung >> diff --git a/drivers/usb/phy/samsung-usbphy.c >> b/drivers/usb/phy/samsung-usbphy.c >> index 4ceabe3..621348a 100644 >> --- a/drivers/usb/phy/samsung-usbphy.c >> +++ b/drivers/usb/phy/samsung-usbphy.c >> @@ -5,7 +5,8 @@ >> * >> * Author: Praveen Paneri >> * >> - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller >> + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and >> + * OHCI-EXYNOS controllers. >> * >> * This program is free software; you can redistribute it and/or modify >> * it under the terms of the GNU General Public License version 2 as >> @@ -24,7 +25,7 @@ >> #include >> #include >> #include >> -#include >> +#include >> #include >> >> /* Register definitions */ >> @@ -56,6 +57,103 @@ >> #define RSTCON_HLINK_SWRST (0x1 << 1) >> #define RSTCON_SWRST (0x1 << 0) >> >> +/* EXYNOS5 */ >> +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) >> + >> +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) >> + >> +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) >> +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) >> +#define
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug, Sorry!! for the delayed response. On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson diand...@chromium.org wrote: Vivek, I don't really have a good 1 foot view about how all of the USB bits fit together, but a few detail-oriented comments below. On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam gautam.vi...@samsung.com wrote: This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri p.pan...@samsung.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be samsung,exynos4210-usbphy - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be samsung,exynos5250-usbphy +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be samsung,usbdev-phyctrl for - DEVICE type phy. + DEVICE type phy; or + should be samsung,usbhost-phyctrl for + HOST type phy; or + should be samsung,usb-phycfg for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri p.pan...@samsung.com * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include linux/err.h #include linux/io.h #include linux/of.h -#include linux/usb/otg.h +#include linux/usb/samsung_usb_phy.h #include linux/platform_data/samsung-usbphy.h /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 1) #define RSTCON_SWRST (0x1 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19) +#define HOST_CTRL0_REFCLKSEL_EXTL
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi, On Fri, Jan 11, 2013 at 06:10:48PM +0530, Vivek Gautam wrote: Hi Doug, Sorry!! for the delayed response. On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson diand...@chromium.org wrote: Vivek, I don't really have a good 1 foot view about how all of the USB bits fit together, but a few detail-oriented comments below. On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam gautam.vi...@samsung.com wrote: This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri p.pan...@samsung.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be samsung,exynos4210-usbphy - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be samsung,exynos5250-usbphy +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be samsung,usbdev-phyctrl for - DEVICE type phy. + DEVICE type phy; or + should be samsung,usbhost-phyctrl for + HOST type phy; or + should be samsung,usb-phycfg for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri p.pan...@samsung.com * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include linux/err.h #include linux/io.h #include linux/of.h -#include linux/usb/otg.h +#include linux/usb/samsung_usb_phy.h #include linux/platform_data/samsung-usbphy.h /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 1) #define RSTCON_SWRST (0x1 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Felipe, On Fri, Jan 11, 2013 at 6:28 PM, Felipe Balbi ba...@ti.com wrote: Hi, On Fri, Jan 11, 2013 at 06:10:48PM +0530, Vivek Gautam wrote: Hi Doug, Sorry!! for the delayed response. On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson diand...@chromium.org wrote: Vivek, I don't really have a good 1 foot view about how all of the USB bits fit together, but a few detail-oriented comments below. On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam gautam.vi...@samsung.com wrote: This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri p.pan...@samsung.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be samsung,exynos4210-usbphy - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be samsung,exynos5250-usbphy +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be samsung,usbdev-phyctrl for - DEVICE type phy. + DEVICE type phy; or + should be samsung,usbhost-phyctrl for + HOST type phy; or + should be samsung,usb-phycfg for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri p.pan...@samsung.com * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include linux/err.h #include linux/io.h #include linux/of.h -#include linux/usb/otg.h +#include linux/usb/samsung_usb_phy.h #include linux/platform_data/samsung-usbphy.h /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 1) #define RSTCON_SWRST (0x1 0) +/*
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Vivek,
On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam gautamvivek1...@gmail.com wrote:
+#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
+#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19)
+#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 19)
+#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 19)
+
+#define HOST_CTRL0_FSEL_MASK (0x7 16)
+#define HOST_CTRL0_FSEL(_x)((_x) 16)
+#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
+#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
+#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
+#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
+#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
+#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
+#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
makes it match the older phy more closely.
Wouldn't it hamper the readability when shifts are used ??
I mean if we have something like this -
phyhost |= HOST_CTRL0_FSEL(phyclk)
so, if we are using the shifts then
phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M HOST_CTRL0_FSEL_SHIFT)
I was actually suggesting modifying the #defines like this:
#define HOST_CTRL0_FSEL_SHIFT 16
#define HOST_CTRL0_FSEL_MASK (0x7 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 HOST_CTRL0_FSEL_SHIFT)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 HOST_CTRL0_FSEL_SHIFT)
...then the code doesn't need to think about shifts, right?
if (IS_ERR(ref_clk)) {
dev_err(sphy-dev, Failed to get reference clock\n);
return PTR_ERR(ref_clk);
}
- switch (clk_get_rate(ref_clk)) {
- case 12 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_12M;
- break;
- case 24 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_24M;
- break;
- case 48 * MHZ:
- refclk_freq = PHYCLK_CLKSEL_48M;
- break;
- default:
- if (sphy-cpu_type == TYPE_S3C64XX)
- refclk_freq = PHYCLK_CLKSEL_48M;
- else
+ if (sphy-cpu_type == TYPE_EXYNOS5250) {
+ /* set clock frequency for PLL */
+ switch (clk_get_rate(ref_clk)) {
+ case 96 * 10:
nit: change to 9600 * KHZ to match; below too.
sure.
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_9600K;
Why |= with 0?
kept this just to keep things look similar :-). will remove this line,
My comment was about keeping things similar. Right now the 5250 code
has the |= and the non-5250 code doesn't. I don't care which is
picked but the two sides of the if should be symmetric.
See parts of the patch below.
+ break;
+ case 10 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_10M;
+ break;
+ case 12 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_12M;
+ break;
+ case 192 * 10:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_19200K;
+ break;
+ case 20 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_20M;
+ break;
+ case 50 * MHZ:
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_50M;
+ break;
+ case 24 * MHZ:
+ default:
+ /* default reference clock */
+ refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_24M;
+ break;
+ }
+ } else {
+ switch (clk_get_rate(ref_clk)) {
+ case 12 * MHZ:
+ refclk_freq = PHYCLK_CLKSEL_12M;
+ break;
+ case 24 * MHZ:
refclk_freq = PHYCLK_CLKSEL_24M;
- break;
+ break;
+ case 48 * MHZ:
+ refclk_freq = PHYCLK_CLKSEL_48M;
+ break;
+ default:
+ if (sphy-cpu_type == TYPE_S3C64XX)
+ refclk_freq = PHYCLK_CLKSEL_48M;
+ else
+ refclk_freq = PHYCLK_CLKSEL_24M;
+ break;
+ }
}
clk_put(ref_clk);
return refclk_freq;
}
-Doug
--
To
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Vivek, I don't really have a good 1 foot view about how all of the USB bits fit together, but a few detail-oriented comments below. On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam wrote: > This patch adds host phy support to samsung-usbphy.c and > further adds support for samsung's exynos5250 usb-phy. > > Signed-off-by: Praveen Paneri > Signed-off-by: Vivek Gautam > --- > .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- > drivers/usb/phy/Kconfig|2 +- > drivers/usb/phy/samsung-usbphy.c | 465 > ++-- > include/linux/usb/samsung_usb_phy.h| 13 + > 4 files changed, 454 insertions(+), 51 deletions(-) > > diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > index a7b28b2..2ec5400 100644 > --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > @@ -1,23 +1,38 @@ > * Samsung's usb phy transceiver > > -The Samsung's phy transceiver is used for controlling usb otg phy for > -s3c-hsotg usb device controller. > +The Samsung's phy transceiver is used for controlling usb phy for > +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers > +across Samsung SOCs. > TODO: Adding the PHY binding with controller(s) according to the under > developement generic PHY driver. > > Required properties: > + > +Exynos4210: > - compatible : should be "samsung,exynos4210-usbphy" > - reg : base physical address of the phy registers and length of memory > mapped > region. > > +Exynos5250: > +- compatible : should be "samsung,exynos5250-usbphy" > +- reg : base physical address of the phy registers and length of memory > mapped > + region. > + > Optional properties: > - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which > provides > binding data to enable/disable device PHY handled by > - PMU register. > + PMU register; or to configure usb2.0 phy handled by > + SYSREG. > > Required properties: > - compatible : should be "samsung,usbdev-phyctrl" for > - DEVICE type phy. > + DEVICE type phy; or > + should be "samsung,usbhost-phyctrl" for > + HOST type phy; or > + should be "samsung,usb-phycfg" for > + USB2.0 PHY_CFG. > - samsung,phyhandle-reg: base physical address of > - PHY_CONTROL register in PMU. > +PHY_CONTROL register in PMU; > +or USB2.0 PHY_CFG register > +in SYSREG. > - samsung,enable-mask : should be '1' > diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig > index 17ad743..13c0eaf 100644 > --- a/drivers/usb/phy/Kconfig > +++ b/drivers/usb/phy/Kconfig > @@ -47,7 +47,7 @@ config USB_RCAR_PHY > > config SAMSUNG_USBPHY > bool "Samsung USB PHY controller Driver" > - depends on USB_S3C_HSOTG > + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS > select USB_OTG_UTILS > help > Enable this to support Samsung USB phy controller for samsung > diff --git a/drivers/usb/phy/samsung-usbphy.c > b/drivers/usb/phy/samsung-usbphy.c > index 4ceabe3..621348a 100644 > --- a/drivers/usb/phy/samsung-usbphy.c > +++ b/drivers/usb/phy/samsung-usbphy.c > @@ -5,7 +5,8 @@ > * > * Author: Praveen Paneri > * > - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller > + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and > + * OHCI-EXYNOS controllers. > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License version 2 as > @@ -24,7 +25,7 @@ > #include > #include > #include > -#include > +#include > #include > > /* Register definitions */ > @@ -56,6 +57,103 @@ > #define RSTCON_HLINK_SWRST (0x1 << 1) > #define RSTCON_SWRST (0x1 << 0) > > +/* EXYNOS5 */ > +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) > + > +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) > + > +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) > +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) > +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) > +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) > + > +#define HOST_CTRL0_FSEL_MASK (0x7 << 16) > +#define HOST_CTRL0_FSEL(_x)((_x)
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Vivek, I don't really have a good 1 foot view about how all of the USB bits fit together, but a few detail-oriented comments below. On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam gautam.vi...@samsung.com wrote: This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri p.pan...@samsung.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be samsung,exynos4210-usbphy - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be samsung,exynos5250-usbphy +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be samsung,usbdev-phyctrl for - DEVICE type phy. + DEVICE type phy; or + should be samsung,usbhost-phyctrl for + HOST type phy; or + should be samsung,usb-phycfg for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri p.pan...@samsung.com * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include linux/err.h #include linux/io.h #include linux/of.h -#include linux/usb/otg.h +#include linux/usb/samsung_usb_phy.h #include linux/platform_data/samsung-usbphy.h /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 1) #define RSTCON_SWRST (0x1 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 16)
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
CC: Doug Anderson. On Tue, Dec 18, 2012 at 8:13 PM, Vivek Gautam wrote: > This patch adds host phy support to samsung-usbphy.c and > further adds support for samsung's exynos5250 usb-phy. > > Signed-off-by: Praveen Paneri > Signed-off-by: Vivek Gautam > --- > .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- > drivers/usb/phy/Kconfig|2 +- > drivers/usb/phy/samsung-usbphy.c | 465 > ++-- > include/linux/usb/samsung_usb_phy.h| 13 + > 4 files changed, 454 insertions(+), 51 deletions(-) > > diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > index a7b28b2..2ec5400 100644 > --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt > @@ -1,23 +1,38 @@ > * Samsung's usb phy transceiver > > -The Samsung's phy transceiver is used for controlling usb otg phy for > -s3c-hsotg usb device controller. > +The Samsung's phy transceiver is used for controlling usb phy for > +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers > +across Samsung SOCs. > TODO: Adding the PHY binding with controller(s) according to the under > developement generic PHY driver. > > Required properties: > + > +Exynos4210: > - compatible : should be "samsung,exynos4210-usbphy" > - reg : base physical address of the phy registers and length of memory > mapped > region. > > +Exynos5250: > +- compatible : should be "samsung,exynos5250-usbphy" > +- reg : base physical address of the phy registers and length of memory > mapped > + region. > + > Optional properties: > - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which > provides > binding data to enable/disable device PHY handled by > - PMU register. > + PMU register; or to configure usb2.0 phy handled by > + SYSREG. > > Required properties: > - compatible : should be "samsung,usbdev-phyctrl" for > - DEVICE type phy. > + DEVICE type phy; or > + should be "samsung,usbhost-phyctrl" for > + HOST type phy; or > + should be "samsung,usb-phycfg" for > + USB2.0 PHY_CFG. > - samsung,phyhandle-reg: base physical address of > - PHY_CONTROL register in PMU. > +PHY_CONTROL register in PMU; > +or USB2.0 PHY_CFG register > +in SYSREG. > - samsung,enable-mask : should be '1' > diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig > index 17ad743..13c0eaf 100644 > --- a/drivers/usb/phy/Kconfig > +++ b/drivers/usb/phy/Kconfig > @@ -47,7 +47,7 @@ config USB_RCAR_PHY > > config SAMSUNG_USBPHY > bool "Samsung USB PHY controller Driver" > - depends on USB_S3C_HSOTG > + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS > select USB_OTG_UTILS > help > Enable this to support Samsung USB phy controller for samsung > diff --git a/drivers/usb/phy/samsung-usbphy.c > b/drivers/usb/phy/samsung-usbphy.c > index 4ceabe3..621348a 100644 > --- a/drivers/usb/phy/samsung-usbphy.c > +++ b/drivers/usb/phy/samsung-usbphy.c > @@ -5,7 +5,8 @@ > * > * Author: Praveen Paneri > * > - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller > + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and > + * OHCI-EXYNOS controllers. > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License version 2 as > @@ -24,7 +25,7 @@ > #include > #include > #include > -#include > +#include > #include > > /* Register definitions */ > @@ -56,6 +57,103 @@ > #define RSTCON_HLINK_SWRST (0x1 << 1) > #define RSTCON_SWRST (0x1 << 0) > > +/* EXYNOS5 */ > +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) > + > +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) > + > +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) > +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) > +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) > +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) > + > +#define HOST_CTRL0_FSEL_MASK (0x7 << 16) > +#define HOST_CTRL0_FSEL(_x)((_x) << 16) > +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7) > +#define HOST_CTRL0_FSEL_CLKSEL_24M
[PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri Signed-off-by: Vivek Gautam --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be "samsung,exynos4210-usbphy" - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be "samsung,exynos5250-usbphy" +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be "samsung,usbdev-phyctrl" for - DEVICE type phy. + DEVICE type phy; or + should be "samsung,usbhost-phyctrl" for + HOST type phy; or + should be "samsung,usb-phycfg" for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool "Samsung USB PHY controller Driver" - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include #include #include -#include +#include #include /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 << 1) #define RSTCON_SWRST (0x1 << 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 << 16) +#define HOST_CTRL0_FSEL(_x)((_x) << 16) +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7) +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5) +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4) +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3) +#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2) +#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1) +#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0) + +#define HOST_CTRL0_TESTBURNIN
[PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri p.pan...@samsung.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be samsung,exynos4210-usbphy - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be samsung,exynos5250-usbphy +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be samsung,usbdev-phyctrl for - DEVICE type phy. + DEVICE type phy; or + should be samsung,usbhost-phyctrl for + HOST type phy; or + should be samsung,usb-phycfg for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri p.pan...@samsung.com * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include linux/err.h #include linux/io.h #include linux/of.h -#include linux/usb/otg.h +#include linux/usb/samsung_usb_phy.h #include linux/platform_data/samsung-usbphy.h /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 1) #define RSTCON_SWRST (0x1 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 16) +#define HOST_CTRL0_FSEL(_x)((_x) 16) +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7) +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5) +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4) +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3) +#define HOST_CTRL0_FSEL_CLKSEL_12M
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
CC: Doug Anderson. On Tue, Dec 18, 2012 at 8:13 PM, Vivek Gautam gautam.vi...@samsung.com wrote: This patch adds host phy support to samsung-usbphy.c and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri p.pan...@samsung.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 465 ++-- include/linux/usb/samsung_usb_phy.h| 13 + 4 files changed, 454 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index a7b28b2..2ec5400 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,23 +1,38 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be samsung,exynos4210-usbphy - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be samsung,exynos5250-usbphy +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which provides binding data to enable/disable device PHY handled by - PMU register. + PMU register; or to configure usb2.0 phy handled by + SYSREG. Required properties: - compatible : should be samsung,usbdev-phyctrl for - DEVICE type phy. + DEVICE type phy; or + should be samsung,usbhost-phyctrl for + HOST type phy; or + should be samsung,usb-phycfg for + USB2.0 PHY_CFG. - samsung,phyhandle-reg: base physical address of - PHY_CONTROL register in PMU. +PHY_CONTROL register in PMU; +or USB2.0 PHY_CFG register +in SYSREG. - samsung,enable-mask : should be '1' diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 17ad743..13c0eaf 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -47,7 +47,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 4ceabe3..621348a 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri p.pan...@samsung.com * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,7 +25,7 @@ #include linux/err.h #include linux/io.h #include linux/of.h -#include linux/usb/otg.h +#include linux/usb/samsung_usb_phy.h #include linux/platform_data/samsung-usbphy.h /* Register definitions */ @@ -56,6 +57,103 @@ #define RSTCON_HLINK_SWRST (0x1 1) #define RSTCON_SWRST (0x1 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 16) +#define HOST_CTRL0_FSEL(_x)((_x) 16) +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
