The CPU clock has had so far a bunch of quirks to expose the clock tree
properly, but since we reverted to exposing them through the MMIO driver,
we can remove that code from the firmware driver.
Acked-by: Nicolas Saenz Julienne
Tested-by: Nicolas Saenz Julienne
Signed-off-by: Maxime Ripard
---
drivers/clk/bcm/clk-raspberrypi.c | 164 +---
1 file changed, 164 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c
b/drivers/clk/bcm/clk-raspberrypi.c
index adc0bb56008a..5cc82954e1ce 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -56,14 +56,6 @@ static char *rpi_firmware_clk_names[] = {
#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
#define RPI_FIRMWARE_STATE_WAIT_BITBIT(1)
-/*
- * Even though the firmware interface alters 'pllb' the frequencies are
- * provided as per 'pllb_arm'. We need to scale before passing them trough.
- */
-#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2
-
-#define A2W_PLL_FRAC_BITS 20
-
struct raspberrypi_clk {
struct device *dev;
struct rpi_firmware *firmware;
@@ -152,13 +144,6 @@ static unsigned long raspberrypi_fw_get_rate(struct clk_hw
*hw,
return val;
}
-static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
-unsigned long parent_rate)
-{
- return raspberrypi_fw_get_rate(hw, parent_rate) *
- RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
-}
-
static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -177,142 +162,6 @@ static int raspberrypi_fw_set_rate(struct clk_hw *hw,
unsigned long rate,
return ret;
}
-static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
-
- return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);
-}
-
-/*
- * Sadly there is no firmware rate rounding interface. We borrowed it from
- * clk-bcm2835.
- */
-static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- u64 div, final_rate;
- u32 ndiv, fdiv;
-
- /* We can't use req->rate directly as it would overflow */
- final_rate = clamp(req->rate, req->min_rate, req->max_rate);
-
- div = (u64)final_rate << A2W_PLL_FRAC_BITS;
- do_div(div, req->best_parent_rate);
-
- ndiv = div >> A2W_PLL_FRAC_BITS;
- fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
-
- final_rate = ((u64)req->best_parent_rate *
- ((ndiv << A2W_PLL_FRAC_BITS) + fdiv));
-
- req->rate = final_rate >> A2W_PLL_FRAC_BITS;
-
- return 0;
-}
-
-static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
- .is_prepared = raspberrypi_fw_is_prepared,
- .recalc_rate = raspberrypi_fw_pll_get_rate,
- .set_rate = raspberrypi_fw_pll_set_rate,
- .determine_rate = raspberrypi_pll_determine_rate,
-};
-
-static struct clk_hw *raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
-{
- struct raspberrypi_clk_data *data;
- struct clk_init_data init = {};
- u32 min_rate = 0, max_rate = 0;
- int ret;
-
- data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return ERR_PTR(-ENOMEM);
- data->rpi = rpi;
- data->id = RPI_FIRMWARE_ARM_CLK_ID;
-
- /* All of the PLLs derive from the external oscillator. */
- init.parent_names = (const char *[]){ "osc" };
- init.num_parents = 1;
- init.name = "pllb";
- init.ops = _firmware_pll_clk_ops;
- init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
-
- /* Get min & max rates set by the firmware */
- ret = raspberrypi_clock_property(rpi->firmware, data,
-RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
-_rate);
- if (ret) {
- dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
- init.name, ret);
- return ERR_PTR(ret);
- }
-
- ret = raspberrypi_clock_property(rpi->firmware, data,
-RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
-_rate);
- if (ret) {
- dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
- init.name, ret);
- return ERR_PTR(ret);
- }
-
- if (!min_rate || !max_rate) {
- dev_err(rpi->dev, "Unexpected frequency range: min %u, max
%u\n",
- min_rate, max_rate);
- return ERR_PTR(-EINVAL);
- }
-
- dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
-min_rate, max_rate);
-
- data->hw.init =
-
- ret
