Re: [PATCH v5 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller

2021-01-28 Thread Arnd Bergmann 
On Sat, Jan 16, 2021 at 4:34 AM Zhen Lei  wrote:
>
> Add devicetree binding for Hisilicon Kunpeng L3 cache controller.
>
> Signed-off-by: Zhen Lei 
> ---
>  .../arm/hisilicon/kunpeng-l3cache.yaml| 40 +++

Reviewed-by: Arnd Bergmann

[PATCH v5 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller

2021-01-15 Thread Zhen Lei 
Add devicetree binding for Hisilicon Kunpeng L3 cache controller.

Signed-off-by: Zhen Lei 
---
 .../arm/hisilicon/kunpeng-l3cache.yaml| 40 +++
 1 file changed, 40 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml

diff --git 
a/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml 
b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
new file mode 100644
index 000..5bf33c0e4d14b7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/kunpeng-l3cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kunpeng L3 cache controller
+
+maintainers:
+  - Wei Xu 
+
+description: |
+  The Hisilicon Kunpeng L3 outer cache controller supports a maximum of 36-bit
+  physical addresses. The data cached in the L3 outer cache can be operated
+  based on the physical address range or the entire cache.
+
+properties:
+  compatible:
+items:
+  - enum:
+  - hisilicon,kunpeng506-l3cache
+  - hisilicon,kunpeng509-l3cache
+  - const: hisilicon,kunpeng-l3cache
+
+  reg:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+l3cache@f302b000 {
+compatible = "hisilicon,kunpeng509-l3cache", 
"hisilicon,kunpeng-l3cache";
+reg = <0xf302b000 0x1000>;
+};
+...
-- 
2.26.0.106.g9fadedd