[PATCH v5 3/4] dt-bindings: clock: Add bindings for ZynqMP clock driver
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP clock driver
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
Reviewed-by: Stephen Boyd
---
.../firmware/xilinx/xlnx,zynqmp-firmware.txt | 53 ++
include/dt-bindings/clock/xlnx,zynqmp-clk.h| 116 +
2 files changed, 169 insertions(+)
create mode 100644 include/dt-bindings/clock/xlnx,zynqmp-clk.h
diff --git
a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
index 1b431d9..614bac5 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
@@ -17,6 +17,53 @@ Required properties:
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
+--
+Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
+Zynq MPSoC firmware interface
+--
+The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
+tree. It reads required input clock frequencies from the devicetree and acts
+as clock provider for all clock consumers of PS clocks.
+
+See clock_bindings.txt for more information on the generic clock bindings.
+
+Required properties:
+ - #clock-cells: Must be 1
+ - compatible: Must contain: "xlnx,zynqmp-clk"
+ - clocks: List of clock specifiers which are external input
+ clocks to the given clock controller. Please refer
+ the next section to find the input clocks for a
+ given controller.
+ - clock-names:List of clock names which are exteral input
clocks
+ to the given clock controller. Please refer to the
+ clock bindings for more details.
+
+Input clocks for zynqmp Ultrascale+ clock controller:
+
+The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
+inputs. These required clock inputs are:
+ - pss_ref_clk (PS reference clock)
+ - video_clk (reference clock for video system )
+ - pss_alt_ref_clk (alternative PS reference clock)
+ - aux_ref_clk
+ - gt_crx_ref_clk (transceiver reference clock)
+
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source:
+ - swdt0_ext_clk
+ - swdt1_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - gem2_emio_clk
+ - gem3_emio_clk
+ - mio_clk_XX # with XX = 00..77
+ - mio_clk_50_or_51#for the mux clock to gem tsu from 50 or 51
+
+
+Output clocks are registered based on clock information received
+from firmware. Output clocks indexes are mentioned in
+include/dt-bindings/clock/xlnx,zynqmp-clk.h.
+
---
Example
---
@@ -25,5 +72,11 @@ firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
+ zynqmp_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <_ref_clk>, <_clk>,
<_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk",
"pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
+ };
};
};
diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h
b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
new file mode 100644
index 000..4aebe6e
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq MPSoC Firmware layer
+ *
+ * Copyright (C) 2014-2018 Xilinx, Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
+#define _DT_BINDINGS_CLK_ZYNQMP_H
+
+#define IOPLL 0
+#define RPLL 1
+#define APLL 2
+#define DPLL 3
+#define VPLL 4
+#define IOPLL_TO_FPD 5
+#define RPLL_TO_FPD6
+#define APLL_TO_LPD7
+#define DPLL_TO_LPD8
+#define VPLL_TO_LPD9
+#define ACPU 10
+#define ACPU_HALF 11
+#define DBF_FPD12
+#define DBF_LPD13
+#define DBG_TRACE 14
+#define DBG_TSTMP 15
+#define DP_VIDEO_REF 16
+#define DP_AUDIO_REF 17
+#define DP_STC_REF 18
+#define GDMA_REF 19
+#define DPDMA_REF 20
+#define DDR_REF21
+#define SATA_REF 22
+#define PCIE_REF 23
+#define GPU_REF24
+#define GPU_PP0_REF25
+#define GPU_PP1_REF26
[PATCH v5 3/4] dt-bindings: clock: Add bindings for ZynqMP clock driver
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP clock driver
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
Reviewed-by: Stephen Boyd
---
.../firmware/xilinx/xlnx,zynqmp-firmware.txt | 53 ++
include/dt-bindings/clock/xlnx,zynqmp-clk.h| 116 +
2 files changed, 169 insertions(+)
create mode 100644 include/dt-bindings/clock/xlnx,zynqmp-clk.h
diff --git
a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
index 1b431d9..614bac5 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
@@ -17,6 +17,53 @@ Required properties:
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
+--
+Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
+Zynq MPSoC firmware interface
+--
+The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
+tree. It reads required input clock frequencies from the devicetree and acts
+as clock provider for all clock consumers of PS clocks.
+
+See clock_bindings.txt for more information on the generic clock bindings.
+
+Required properties:
+ - #clock-cells: Must be 1
+ - compatible: Must contain: "xlnx,zynqmp-clk"
+ - clocks: List of clock specifiers which are external input
+ clocks to the given clock controller. Please refer
+ the next section to find the input clocks for a
+ given controller.
+ - clock-names:List of clock names which are exteral input
clocks
+ to the given clock controller. Please refer to the
+ clock bindings for more details.
+
+Input clocks for zynqmp Ultrascale+ clock controller:
+
+The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
+inputs. These required clock inputs are:
+ - pss_ref_clk (PS reference clock)
+ - video_clk (reference clock for video system )
+ - pss_alt_ref_clk (alternative PS reference clock)
+ - aux_ref_clk
+ - gt_crx_ref_clk (transceiver reference clock)
+
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source:
+ - swdt0_ext_clk
+ - swdt1_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - gem2_emio_clk
+ - gem3_emio_clk
+ - mio_clk_XX # with XX = 00..77
+ - mio_clk_50_or_51#for the mux clock to gem tsu from 50 or 51
+
+
+Output clocks are registered based on clock information received
+from firmware. Output clocks indexes are mentioned in
+include/dt-bindings/clock/xlnx,zynqmp-clk.h.
+
---
Example
---
@@ -25,5 +72,11 @@ firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
+ zynqmp_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <_ref_clk>, <_clk>,
<_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk",
"pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
+ };
};
};
diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h
b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
new file mode 100644
index 000..4aebe6e
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq MPSoC Firmware layer
+ *
+ * Copyright (C) 2014-2018 Xilinx, Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
+#define _DT_BINDINGS_CLK_ZYNQMP_H
+
+#define IOPLL 0
+#define RPLL 1
+#define APLL 2
+#define DPLL 3
+#define VPLL 4
+#define IOPLL_TO_FPD 5
+#define RPLL_TO_FPD6
+#define APLL_TO_LPD7
+#define DPLL_TO_LPD8
+#define VPLL_TO_LPD9
+#define ACPU 10
+#define ACPU_HALF 11
+#define DBF_FPD12
+#define DBF_LPD13
+#define DBG_TRACE 14
+#define DBG_TSTMP 15
+#define DP_VIDEO_REF 16
+#define DP_AUDIO_REF 17
+#define DP_STC_REF 18
+#define GDMA_REF 19
+#define DPDMA_REF 20
+#define DDR_REF21
+#define SATA_REF 22
+#define PCIE_REF 23
+#define GPU_REF24
+#define GPU_PP0_REF25
+#define GPU_PP1_REF26
