Re: [PATCH v5 5/9] drm/i915: Add HDCP framework + base implementation

[Philippe Ombredanne]

Sean,

On Mon, Jan 8, 2018 at 4:50 PM, Sean Paul  wrote:
> This patch adds the framework required to add HDCP support to intel
> connectors. It implements Aksv loading from fuse, and parts 1/2/3
> of the HDCP authentication scheme.
>
> Note that without shim implementations, this does not actually implement
> HDCP. That will come in subsequent patches.



> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -0,0 +1,740 @@
> +/*
> + * Copyright (C) 2017 Google, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.

Would you mind using an SPDX tag instead of this fine but long legalese?
See Thomas doc [1] for details.
Thanks!

[1] https://lkml.org/lkml/2017/12/28/323
-- 
Cordially
Philippe Ombredanne

Re: [PATCH v5 5/9] drm/i915: Add HDCP framework + base implementation

[Philippe Ombredanne]

Sean,

On Mon, Jan 8, 2018 at 4:50 PM, Sean Paul  wrote:
> This patch adds the framework required to add HDCP support to intel
> connectors. It implements Aksv loading from fuse, and parts 1/2/3
> of the HDCP authentication scheme.
>
> Note that without shim implementations, this does not actually implement
> HDCP. That will come in subsequent patches.



> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -0,0 +1,740 @@
> +/*
> + * Copyright (C) 2017 Google, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.

Would you mind using an SPDX tag instead of this fine but long legalese?
See Thomas doc [1] for details.
Thanks!

[1] https://lkml.org/lkml/2017/12/28/323
-- 
Cordially
Philippe Ombredanne

[PATCH v5 5/9] drm/i915: Add HDCP framework + base implementation

[Sean Paul]

This patch adds the framework required to add HDCP support to intel
connectors. It implements Aksv loading from fuse, and parts 1/2/3
of the HDCP authentication scheme.

Note that without shim implementations, this does not actually implement
HDCP. That will come in subsequent patches.

Changes in v2:
- Don't open code wait_fors (Chris)
- drm_hdcp.c under MIT license (Daniel)
- Move intel_hdcp_disable() call above ddi_disable (Ram)
- Fix // comments (I wore a cone of shame for 12 hours to atone) (Daniel)
- Justify intel_hdcp_shim with comments (Daniel)
- Fixed async locking issues by adding hdcp_mutex (Daniel)
- Don't alter connector_state in enable/disable (Daniel)
Changes in v3:
- Added hdcp_mutex/hdcp_value to make async reasonable
- Added hdcp_prop_work to separate link checking & property setting
- Added new helper for atomic_check state tracking (Daniel)
- Moved enable/disable into atomic_commit with matching helpers
- Moved intel_hdcp_check_link out of all locks when called from dp
- Bumped up ksv_fifo timeout (noticed failure on one of my dongles)
Changes in v4:
- Remove SKL_ prefix from most register names (Daniel)
- Move enable/disable back to modeset path (Daniel)
- s/get_random_long/get_random_u32/ (Daniel)
- Remove mode_config.mutex lock in prop_work (Daniel)
- Add intel_hdcp_init to handle init of conn components (Daniel)
- Actually check return value of attach_property
- Check Bksv is valid before trying to authenticate (Ram)
Changes in v5:
- checkpatch whitespace changes
- s/DRM_MODE_CONTENT_PROTECTION_OFF/DRM_MODE_CONTENT_PROTECTION_UNDESIRED/
- Fix ksv list wait timeout (actually wait 5s)
- Increase the R0 timeout to 300ms (Ram)

Cc: Chris Wilson 
Reviewed-by: Ramalingam C 
Reviewed-by: Daniel Vetter 
Signed-off-by: Sean Paul 
---
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_reg.h  |  83 
 drivers/gpu/drm/i915/intel_atomic.c  |   2 +
 drivers/gpu/drm/i915/intel_ddi.c |   7 +
 drivers/gpu/drm/i915/intel_display.c |   4 +
 drivers/gpu/drm/i915/intel_drv.h |  85 
 drivers/gpu/drm/i915/intel_hdcp.c| 740 +++
 7 files changed, 922 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4d9e2f855e9d..3bddd8a06806 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -109,6 +109,7 @@ i915-y += intel_audio.o \
  intel_fbc.o \
  intel_fifo_underrun.o \
  intel_frontbuffer.o \
+ intel_hdcp.o \
  intel_hotplug.o \
  intel_modes.o \
  intel_overlay.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 505c605eff98..5db8d18c73ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8046,6 +8046,7 @@ enum {
 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT   8
 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT   16
 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT   24
+#define   SKL_PCODE_LOAD_HDCP_KEYS 0x5
 #define   SKL_PCODE_CDCLK_CONTROL  0x7
 #define SKL_CDCLK_PREPARE_FOR_CHANGE   0x3
 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
@@ -8348,6 +8349,88 @@ enum skl_power_gate {
 #define  SKL_PW_TO_PG(pw)  ((pw) - SKL_DISP_PW_1 + SKL_PG1)
 #define  SKL_FUSE_PG_DIST_STATUS(pg)   (1 << (27 - (pg)))
 
+
+/* HDCP Key Registers */
+#define HDCP_KEY_CONF  _MMIO(0x66c00)
+#define  HDCP_AKSV_SEND_TRIGGERBIT(31)
+#define  HDCP_CLEAR_KEYS_TRIGGER   BIT(30)
+#define HDCP_KEY_STATUS_MMIO(0x66c04)
+#define  HDCP_FUSE_IN_PROGRESS BIT(7)
+#define  HDCP_FUSE_ERROR   BIT(6)
+#define  HDCP_FUSE_DONEBIT(5)
+#define  HDCP_KEY_LOAD_STATUS  BIT(1)
+#define  HDCP_KEY_LOAD_DONEBIT(0)
+#define HDCP_AKSV_LO   _MMIO(0x66c10)
+#define HDCP_AKSV_HI   _MMIO(0x66c14)
+
+/* HDCP Repeater Registers */
+#define HDCP_REP_CTL   _MMIO(0x66d00)
+#define  HDCP_DDIB_REP_PRESENT BIT(30)
+#define  HDCP_DDIA_REP_PRESENT BIT(29)
+#define  HDCP_DDIC_REP_PRESENT BIT(28)
+#define  HDCP_DDID_REP_PRESENT BIT(27)
+#define  HDCP_DDIF_REP_PRESENT BIT(26)
+#define  HDCP_DDIE_REP_PRESENT BIT(25)
+#define  HDCP_DDIB_SHA1_M0 (1 << 20)
+#define  HDCP_DDIA_SHA1_M0 (2 << 20)
+#define  HDCP_DDIC_SHA1_M0 (3 << 20)
+#define  HDCP_DDID_SHA1_M0 (4 << 20)
+#define  HDCP_DDIF_SHA1_M0 (5 << 20)
+#define  HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
+#define  HDCP_SHA1_BUSYBIT(16)
+#define  HDCP_SHA1_READY   BIT(17)
+#define  HDCP_SHA1_COMPLETEBIT(18)
+#define  HDCP_SHA1_V_MATCH BIT(19)
+#define  HDCP_SHA1_TEXT_32 (1 << 1)
+#define  HDCP_SHA1_COMPLETE_HASH 

[PATCH v5 5/9] drm/i915: Add HDCP framework + base implementation

[Sean Paul]

This patch adds the framework required to add HDCP support to intel
connectors. It implements Aksv loading from fuse, and parts 1/2/3
of the HDCP authentication scheme.

Note that without shim implementations, this does not actually implement
HDCP. That will come in subsequent patches.

Changes in v2:
- Don't open code wait_fors (Chris)
- drm_hdcp.c under MIT license (Daniel)
- Move intel_hdcp_disable() call above ddi_disable (Ram)
- Fix // comments (I wore a cone of shame for 12 hours to atone) (Daniel)
- Justify intel_hdcp_shim with comments (Daniel)
- Fixed async locking issues by adding hdcp_mutex (Daniel)
- Don't alter connector_state in enable/disable (Daniel)
Changes in v3:
- Added hdcp_mutex/hdcp_value to make async reasonable
- Added hdcp_prop_work to separate link checking & property setting
- Added new helper for atomic_check state tracking (Daniel)
- Moved enable/disable into atomic_commit with matching helpers
- Moved intel_hdcp_check_link out of all locks when called from dp
- Bumped up ksv_fifo timeout (noticed failure on one of my dongles)
Changes in v4:
- Remove SKL_ prefix from most register names (Daniel)
- Move enable/disable back to modeset path (Daniel)
- s/get_random_long/get_random_u32/ (Daniel)
- Remove mode_config.mutex lock in prop_work (Daniel)
- Add intel_hdcp_init to handle init of conn components (Daniel)
- Actually check return value of attach_property
- Check Bksv is valid before trying to authenticate (Ram)
Changes in v5:
- checkpatch whitespace changes
- s/DRM_MODE_CONTENT_PROTECTION_OFF/DRM_MODE_CONTENT_PROTECTION_UNDESIRED/
- Fix ksv list wait timeout (actually wait 5s)
- Increase the R0 timeout to 300ms (Ram)

Cc: Chris Wilson 
Reviewed-by: Ramalingam C 
Reviewed-by: Daniel Vetter 
Signed-off-by: Sean Paul 
---
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_reg.h  |  83 
 drivers/gpu/drm/i915/intel_atomic.c  |   2 +
 drivers/gpu/drm/i915/intel_ddi.c |   7 +
 drivers/gpu/drm/i915/intel_display.c |   4 +
 drivers/gpu/drm/i915/intel_drv.h |  85 
 drivers/gpu/drm/i915/intel_hdcp.c| 740 +++
 7 files changed, 922 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4d9e2f855e9d..3bddd8a06806 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -109,6 +109,7 @@ i915-y += intel_audio.o \
  intel_fbc.o \
  intel_fifo_underrun.o \
  intel_frontbuffer.o \
+ intel_hdcp.o \
  intel_hotplug.o \
  intel_modes.o \
  intel_overlay.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 505c605eff98..5db8d18c73ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8046,6 +8046,7 @@ enum {
 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT   8
 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT   16
 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT   24
+#define   SKL_PCODE_LOAD_HDCP_KEYS 0x5
 #define   SKL_PCODE_CDCLK_CONTROL  0x7
 #define SKL_CDCLK_PREPARE_FOR_CHANGE   0x3
 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
@@ -8348,6 +8349,88 @@ enum skl_power_gate {
 #define  SKL_PW_TO_PG(pw)  ((pw) - SKL_DISP_PW_1 + SKL_PG1)
 #define  SKL_FUSE_PG_DIST_STATUS(pg)   (1 << (27 - (pg)))
 
+
+/* HDCP Key Registers */
+#define HDCP_KEY_CONF  _MMIO(0x66c00)
+#define  HDCP_AKSV_SEND_TRIGGERBIT(31)
+#define  HDCP_CLEAR_KEYS_TRIGGER   BIT(30)
+#define HDCP_KEY_STATUS_MMIO(0x66c04)
+#define  HDCP_FUSE_IN_PROGRESS BIT(7)
+#define  HDCP_FUSE_ERROR   BIT(6)
+#define  HDCP_FUSE_DONEBIT(5)
+#define  HDCP_KEY_LOAD_STATUS  BIT(1)
+#define  HDCP_KEY_LOAD_DONEBIT(0)
+#define HDCP_AKSV_LO   _MMIO(0x66c10)
+#define HDCP_AKSV_HI   _MMIO(0x66c14)
+
+/* HDCP Repeater Registers */
+#define HDCP_REP_CTL   _MMIO(0x66d00)
+#define  HDCP_DDIB_REP_PRESENT BIT(30)
+#define  HDCP_DDIA_REP_PRESENT BIT(29)
+#define  HDCP_DDIC_REP_PRESENT BIT(28)
+#define  HDCP_DDID_REP_PRESENT BIT(27)
+#define  HDCP_DDIF_REP_PRESENT BIT(26)
+#define  HDCP_DDIE_REP_PRESENT BIT(25)
+#define  HDCP_DDIB_SHA1_M0 (1 << 20)
+#define  HDCP_DDIA_SHA1_M0 (2 << 20)
+#define  HDCP_DDIC_SHA1_M0 (3 << 20)
+#define  HDCP_DDID_SHA1_M0 (4 << 20)
+#define  HDCP_DDIF_SHA1_M0 (5 << 20)
+#define  HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
+#define  HDCP_SHA1_BUSYBIT(16)
+#define  HDCP_SHA1_READY   BIT(17)
+#define  HDCP_SHA1_COMPLETEBIT(18)
+#define  HDCP_SHA1_V_MATCH BIT(19)
+#define  HDCP_SHA1_TEXT_32 (1 << 1)
+#define  HDCP_SHA1_COMPLETE_HASH   (2 << 1)
+#define  HDCP_SHA1_TEXT_24 (4 << 1)
+#define  HDCP_SHA1_TEXT_16