Add DP device node on sc7180.
Changes in v2:
- Add assigned-clocks and assigned-clock-parents
- Remove cell-index and pixel_rcg
- Change compatible to qcom,sc7180-dp
Changes in v3:
- Update commit text
- Make DP child node of MDSS
- Remove data-lanes property from SOC dts
- Disable DP node in SOC dts
- Assign DP to Port2 in MDP node
- Add MDSS AHB clock in DP device node
Changes in v4:
- Remove redundant reg-names property
- Use IRQ flag instead had hard coded value.
- Add link clock source in assigned-clocks list.
Changes in v5:
- Add OPP table and power-domains for DisplayPort
Changes in v6:
- Remove redundant IRQ flag
Signed-off-by: Tanmay Shah
Co-developed-by: Kuogee Hsieh
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 76 +++-
1 file changed, 74 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 31b9217bb5bf..bf2f2bb1aa79 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2371,6 +2371,13 @@ dpu_intf1_out: endpoint {
remote-endpoint =
<_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
};
};
@@ -2440,6 +2447,71 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled";
};
+
+ msm_dp: displayport-controller@ae9 {
+ status = "disabled";
+ compatible = "qcom,sc7180-dp";
+
+ reg = <0 0x0ae9 0 0x1400>;
+
+ interrupt-parent = <>;
+ interrupts = <12>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_DP_AUX_CLK>,
+< DISP_CC_MDSS_DP_LINK_CLK>,
+<
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+< DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux",
"ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <_dp 0>, <_dp
1>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SC7180_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint =
<_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: dp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-16000 {
+ opp-hz = /bits/ 64 <16000>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64 <27000>;
+ required-opps =
<_opp_svs>;
+ };
+
+ opp-54000 {
+ opp-hz = /bits/ 64 <54000>;
+ required-opps =
<_opp_svs_l1>;
+ };
+
+ opp-81000 {
+ opp-hz = /bits/ 64 <81000>;
+
