Re: [PATCH v6 1/2] spi: Add MXIC controller driver

2018-10-17 Thread Boris Brezillon
On Wed, 17 Oct 2018 10:08:11 +0800
masonccy...@mxic.com.tw wrote:

> From: Mason Yang 
> 
> Add a driver for Macronix SPI controller IP.
> 
> Signed-off-by: Mason Yang 

Reviewed-by: Boris Brezillon 

> ---
>  drivers/spi/Kconfig|   6 +
>  drivers/spi/Makefile   |   1 +
>  drivers/spi/spi-mxic.c | 619 
> +
>  3 files changed, 626 insertions(+)
>  create mode 100644 drivers/spi/spi-mxic.c
> 
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ad5d68e..7e900b5 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -633,6 +633,12 @@ config SPI_SUN6I
>   help
> This enables using the SPI controller on the Allwinner A31 SoCs.
>  
> +config SPI_MXIC
> +tristate "Macronix MX25F0A SPI controller"
> +depends on SPI_MASTER
> +help
> +  This selects the Macronix MX25F0A SPI controller driver.
> +
>  config SPI_MXS
>   tristate "Freescale MXS SPI controller"
>   depends on ARCH_MXS
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index cb1f437..d7a1ceb 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC)   += 
> spi-mpc512x-psc.o
>  obj-$(CONFIG_SPI_MPC52xx_PSC)+= spi-mpc52xx-psc.o
>  obj-$(CONFIG_SPI_MPC52xx)+= spi-mpc52xx.o
>  obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
> +obj-$(CONFIG_SPI_MXIC)   += spi-mxic.o
>  obj-$(CONFIG_SPI_MXS)+= spi-mxs.o
>  obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
>  obj-$(CONFIG_SPI_OC_TINY)+= spi-oc-tiny.o
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> new file mode 100644
> index 000..e41ae6e
> --- /dev/null
> +++ b/drivers/spi/spi-mxic.c
> @@ -0,0 +1,619 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2018 Macronix International Co., Ltd.
> +//
> +// Authors:
> +//   Mason Yang 
> +//   zhengxunli 
> +//   Boris Brezillon 
> +//
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define HC_CFG   0x0
> +#define HC_CFG_IF_CFG(x) ((x) << 27)
> +#define HC_CFG_DUAL_SLAVEBIT(31)
> +#define HC_CFG_INDIVIDUALBIT(30)
> +#define HC_CFG_NIO(x)(((x) / 4) << 27)
> +#define HC_CFG_TYPE(s, t)((t) << (23 + ((s) * 2)))
> +#define HC_CFG_TYPE_SPI_NOR  0
> +#define HC_CFG_TYPE_SPI_NAND 1
> +#define HC_CFG_TYPE_SPI_RAM  2
> +#define HC_CFG_TYPE_RAW_NAND 3
> +#define HC_CFG_SLV_ACT(x)((x) << 21)
> +#define HC_CFG_CLK_PH_EN BIT(20)
> +#define HC_CFG_CLK_POL_INV   BIT(19)
> +#define HC_CFG_BIG_ENDIANBIT(18)
> +#define HC_CFG_DATA_PASS BIT(17)
> +#define HC_CFG_IDLE_SIO_LVL(x)   ((x) << 16)
> +#define HC_CFG_MAN_START_EN  BIT(3)
> +#define HC_CFG_MAN_START BIT(2)
> +#define HC_CFG_MAN_CS_EN BIT(1)
> +#define HC_CFG_MAN_CS_ASSERT BIT(0)
> +
> +#define INT_STS  0x4
> +#define INT_STS_EN   0x8
> +#define INT_SIG_EN   0xc
> +#define INT_STS_ALL  GENMASK(31, 0)
> +#define INT_RDY_PIN  BIT(26)
> +#define INT_RDY_SR   BIT(25)
> +#define INT_LNR_SUSP BIT(24)
> +#define INT_ECC_ERR  BIT(17)
> +#define INT_CRC_ERR  BIT(16)
> +#define INT_LWR_DIS  BIT(12)
> +#define INT_LRD_DIS  BIT(11)
> +#define INT_SDMA_INT BIT(10)
> +#define INT_DMA_FINISH   BIT(9)
> +#define INT_RX_NOT_FULL  BIT(3)
> +#define INT_RX_NOT_EMPTY BIT(2)
> +#define INT_TX_NOT_FULL  BIT(1)
> +#define INT_TX_EMPTY BIT(0)
> +
> +#define HC_EN0x10
> +#define HC_EN_BITBIT(0)
> +
> +#define TXD(x)   (0x14 + ((x) * 4))
> +#define RXD  0x24
> +
> +#define SS_CTRL(s)   (0x30 + ((s) * 4))
> +#define LRD_CFG  0x44
> +#define LWR_CFG  0x80
> +#define RWW_CFG  0x70
> +#define OP_READ  BIT(23)
> +#define OP_DUMMY_CYC(x)  ((x) << 17)
> +#define OP_ADDR_BYTES(x) ((x) << 14)
> +#define OP_CMD_BYTES(x)  (((x) - 1) << 13)
> +#define OP_OCTA_CRC_EN   BIT(12)
> +#define OP_DQS_ENBIT(11)
> +#define OP_ENHC_EN   BIT(10)
> +#define OP_PREAMBLE_EN   BIT(9)
> +#define OP_DATA_DDR  BIT(8)
> +#define OP_DATA_BUSW(x)  ((x) << 6)
> +#define OP_ADDR_DDR  BIT(5)
> +#define OP_ADDR_BUSW(x)  ((x) << 3)
> +#define OP_CMD_DDR   BIT(2)
> +#define OP_CMD_BUSW(x)   (x)
> +#define OP_BUSW_10
> +#define OP_BUSW_21
> +#define OP_BUSW_42
> +#define OP_BUSW_83
> +
> +#define OCTA_CRC 0x38
> +#define OCTA_CRC_IN_EN(s)BIT(3 + ((s) * 16))
> +#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + 

Re: [PATCH v6 1/2] spi: Add MXIC controller driver

2018-10-17 Thread Boris Brezillon
On Wed, 17 Oct 2018 10:08:11 +0800
masonccy...@mxic.com.tw wrote:

> From: Mason Yang 
> 
> Add a driver for Macronix SPI controller IP.
> 
> Signed-off-by: Mason Yang 

Reviewed-by: Boris Brezillon 

> ---
>  drivers/spi/Kconfig|   6 +
>  drivers/spi/Makefile   |   1 +
>  drivers/spi/spi-mxic.c | 619 
> +
>  3 files changed, 626 insertions(+)
>  create mode 100644 drivers/spi/spi-mxic.c
> 
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ad5d68e..7e900b5 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -633,6 +633,12 @@ config SPI_SUN6I
>   help
> This enables using the SPI controller on the Allwinner A31 SoCs.
>  
> +config SPI_MXIC
> +tristate "Macronix MX25F0A SPI controller"
> +depends on SPI_MASTER
> +help
> +  This selects the Macronix MX25F0A SPI controller driver.
> +
>  config SPI_MXS
>   tristate "Freescale MXS SPI controller"
>   depends on ARCH_MXS
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index cb1f437..d7a1ceb 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC)   += 
> spi-mpc512x-psc.o
>  obj-$(CONFIG_SPI_MPC52xx_PSC)+= spi-mpc52xx-psc.o
>  obj-$(CONFIG_SPI_MPC52xx)+= spi-mpc52xx.o
>  obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
> +obj-$(CONFIG_SPI_MXIC)   += spi-mxic.o
>  obj-$(CONFIG_SPI_MXS)+= spi-mxs.o
>  obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
>  obj-$(CONFIG_SPI_OC_TINY)+= spi-oc-tiny.o
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> new file mode 100644
> index 000..e41ae6e
> --- /dev/null
> +++ b/drivers/spi/spi-mxic.c
> @@ -0,0 +1,619 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2018 Macronix International Co., Ltd.
> +//
> +// Authors:
> +//   Mason Yang 
> +//   zhengxunli 
> +//   Boris Brezillon 
> +//
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define HC_CFG   0x0
> +#define HC_CFG_IF_CFG(x) ((x) << 27)
> +#define HC_CFG_DUAL_SLAVEBIT(31)
> +#define HC_CFG_INDIVIDUALBIT(30)
> +#define HC_CFG_NIO(x)(((x) / 4) << 27)
> +#define HC_CFG_TYPE(s, t)((t) << (23 + ((s) * 2)))
> +#define HC_CFG_TYPE_SPI_NOR  0
> +#define HC_CFG_TYPE_SPI_NAND 1
> +#define HC_CFG_TYPE_SPI_RAM  2
> +#define HC_CFG_TYPE_RAW_NAND 3
> +#define HC_CFG_SLV_ACT(x)((x) << 21)
> +#define HC_CFG_CLK_PH_EN BIT(20)
> +#define HC_CFG_CLK_POL_INV   BIT(19)
> +#define HC_CFG_BIG_ENDIANBIT(18)
> +#define HC_CFG_DATA_PASS BIT(17)
> +#define HC_CFG_IDLE_SIO_LVL(x)   ((x) << 16)
> +#define HC_CFG_MAN_START_EN  BIT(3)
> +#define HC_CFG_MAN_START BIT(2)
> +#define HC_CFG_MAN_CS_EN BIT(1)
> +#define HC_CFG_MAN_CS_ASSERT BIT(0)
> +
> +#define INT_STS  0x4
> +#define INT_STS_EN   0x8
> +#define INT_SIG_EN   0xc
> +#define INT_STS_ALL  GENMASK(31, 0)
> +#define INT_RDY_PIN  BIT(26)
> +#define INT_RDY_SR   BIT(25)
> +#define INT_LNR_SUSP BIT(24)
> +#define INT_ECC_ERR  BIT(17)
> +#define INT_CRC_ERR  BIT(16)
> +#define INT_LWR_DIS  BIT(12)
> +#define INT_LRD_DIS  BIT(11)
> +#define INT_SDMA_INT BIT(10)
> +#define INT_DMA_FINISH   BIT(9)
> +#define INT_RX_NOT_FULL  BIT(3)
> +#define INT_RX_NOT_EMPTY BIT(2)
> +#define INT_TX_NOT_FULL  BIT(1)
> +#define INT_TX_EMPTY BIT(0)
> +
> +#define HC_EN0x10
> +#define HC_EN_BITBIT(0)
> +
> +#define TXD(x)   (0x14 + ((x) * 4))
> +#define RXD  0x24
> +
> +#define SS_CTRL(s)   (0x30 + ((s) * 4))
> +#define LRD_CFG  0x44
> +#define LWR_CFG  0x80
> +#define RWW_CFG  0x70
> +#define OP_READ  BIT(23)
> +#define OP_DUMMY_CYC(x)  ((x) << 17)
> +#define OP_ADDR_BYTES(x) ((x) << 14)
> +#define OP_CMD_BYTES(x)  (((x) - 1) << 13)
> +#define OP_OCTA_CRC_EN   BIT(12)
> +#define OP_DQS_ENBIT(11)
> +#define OP_ENHC_EN   BIT(10)
> +#define OP_PREAMBLE_EN   BIT(9)
> +#define OP_DATA_DDR  BIT(8)
> +#define OP_DATA_BUSW(x)  ((x) << 6)
> +#define OP_ADDR_DDR  BIT(5)
> +#define OP_ADDR_BUSW(x)  ((x) << 3)
> +#define OP_CMD_DDR   BIT(2)
> +#define OP_CMD_BUSW(x)   (x)
> +#define OP_BUSW_10
> +#define OP_BUSW_21
> +#define OP_BUSW_42
> +#define OP_BUSW_83
> +
> +#define OCTA_CRC 0x38
> +#define OCTA_CRC_IN_EN(s)BIT(3 + ((s) * 16))
> +#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + 

[PATCH v6 1/2] spi: Add MXIC controller driver

2018-10-16 Thread masonccyang
From: Mason Yang 

Add a driver for Macronix SPI controller IP.

Signed-off-by: Mason Yang 
---
 drivers/spi/Kconfig|   6 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-mxic.c | 619 +
 3 files changed, 626 insertions(+)
 create mode 100644 drivers/spi/spi-mxic.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ad5d68e..7e900b5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -633,6 +633,12 @@ config SPI_SUN6I
help
  This enables using the SPI controller on the Allwinner A31 SoCs.
 
+config SPI_MXIC
+tristate "Macronix MX25F0A SPI controller"
+depends on SPI_MASTER
+help
+  This selects the Macronix MX25F0A SPI controller driver.
+
 config SPI_MXS
tristate "Freescale MXS SPI controller"
depends on ARCH_MXS
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cb1f437..d7a1ceb 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)  += spi-mpc52xx.o
 obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
+obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
 obj-$(CONFIG_SPI_MXS)  += spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)   += spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)  += spi-oc-tiny.o
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
new file mode 100644
index 000..e41ae6e
--- /dev/null
+++ b/drivers/spi/spi-mxic.c
@@ -0,0 +1,619 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2018 Macronix International Co., Ltd.
+//
+// Authors:
+// Mason Yang 
+// zhengxunli 
+// Boris Brezillon 
+//
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HC_CFG 0x0
+#define HC_CFG_IF_CFG(x)   ((x) << 27)
+#define HC_CFG_DUAL_SLAVE  BIT(31)
+#define HC_CFG_INDIVIDUAL  BIT(30)
+#define HC_CFG_NIO(x)  (((x) / 4) << 27)
+#define HC_CFG_TYPE(s, t)  ((t) << (23 + ((s) * 2)))
+#define HC_CFG_TYPE_SPI_NOR0
+#define HC_CFG_TYPE_SPI_NAND   1
+#define HC_CFG_TYPE_SPI_RAM2
+#define HC_CFG_TYPE_RAW_NAND   3
+#define HC_CFG_SLV_ACT(x)  ((x) << 21)
+#define HC_CFG_CLK_PH_EN   BIT(20)
+#define HC_CFG_CLK_POL_INV BIT(19)
+#define HC_CFG_BIG_ENDIAN  BIT(18)
+#define HC_CFG_DATA_PASS   BIT(17)
+#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
+#define HC_CFG_MAN_START_ENBIT(3)
+#define HC_CFG_MAN_START   BIT(2)
+#define HC_CFG_MAN_CS_EN   BIT(1)
+#define HC_CFG_MAN_CS_ASSERT   BIT(0)
+
+#define INT_STS0x4
+#define INT_STS_EN 0x8
+#define INT_SIG_EN 0xc
+#define INT_STS_ALLGENMASK(31, 0)
+#define INT_RDY_PINBIT(26)
+#define INT_RDY_SR BIT(25)
+#define INT_LNR_SUSP   BIT(24)
+#define INT_ECC_ERRBIT(17)
+#define INT_CRC_ERRBIT(16)
+#define INT_LWR_DISBIT(12)
+#define INT_LRD_DISBIT(11)
+#define INT_SDMA_INT   BIT(10)
+#define INT_DMA_FINISH BIT(9)
+#define INT_RX_NOT_FULLBIT(3)
+#define INT_RX_NOT_EMPTY   BIT(2)
+#define INT_TX_NOT_FULLBIT(1)
+#define INT_TX_EMPTY   BIT(0)
+
+#define HC_EN  0x10
+#define HC_EN_BIT  BIT(0)
+
+#define TXD(x) (0x14 + ((x) * 4))
+#define RXD0x24
+
+#define SS_CTRL(s) (0x30 + ((s) * 4))
+#define LRD_CFG0x44
+#define LWR_CFG0x80
+#define RWW_CFG0x70
+#define OP_READBIT(23)
+#define OP_DUMMY_CYC(x)((x) << 17)
+#define OP_ADDR_BYTES(x)   ((x) << 14)
+#define OP_CMD_BYTES(x)(((x) - 1) << 13)
+#define OP_OCTA_CRC_EN BIT(12)
+#define OP_DQS_EN  BIT(11)
+#define OP_ENHC_EN BIT(10)
+#define OP_PREAMBLE_EN BIT(9)
+#define OP_DATA_DDRBIT(8)
+#define OP_DATA_BUSW(x)((x) << 6)
+#define OP_ADDR_DDRBIT(5)
+#define OP_ADDR_BUSW(x)((x) << 3)
+#define OP_CMD_DDR BIT(2)
+#define OP_CMD_BUSW(x) (x)
+#define OP_BUSW_1  0
+#define OP_BUSW_2  1
+#define OP_BUSW_4  2
+#define OP_BUSW_8  3
+
+#define OCTA_CRC   0x38
+#define OCTA_CRC_IN_EN(s)  BIT(3 + ((s) * 16))
+#define OCTA_CRC_CHUNK(s, x)   ((fls((x) / 32)) << (1 + ((s) * 16)))
+#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
+
+#define ONFI_DIN_CNT(s)(0x3c + (s))
+
+#define LRD_CTRL   0x48
+#define RWW_CTRL   0x74
+#define LWR_CTRL   0x84
+#define LMODE_EN   BIT(31)
+#define LMODE_SLV_ACT(x)   ((x) << 21)

[PATCH v6 1/2] spi: Add MXIC controller driver

2018-10-16 Thread masonccyang
From: Mason Yang 

Add a driver for Macronix SPI controller IP.

Signed-off-by: Mason Yang 
---
 drivers/spi/Kconfig|   6 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-mxic.c | 619 +
 3 files changed, 626 insertions(+)
 create mode 100644 drivers/spi/spi-mxic.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ad5d68e..7e900b5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -633,6 +633,12 @@ config SPI_SUN6I
help
  This enables using the SPI controller on the Allwinner A31 SoCs.
 
+config SPI_MXIC
+tristate "Macronix MX25F0A SPI controller"
+depends on SPI_MASTER
+help
+  This selects the Macronix MX25F0A SPI controller driver.
+
 config SPI_MXS
tristate "Freescale MXS SPI controller"
depends on ARCH_MXS
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cb1f437..d7a1ceb 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)  += spi-mpc52xx.o
 obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
+obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
 obj-$(CONFIG_SPI_MXS)  += spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)   += spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)  += spi-oc-tiny.o
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
new file mode 100644
index 000..e41ae6e
--- /dev/null
+++ b/drivers/spi/spi-mxic.c
@@ -0,0 +1,619 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2018 Macronix International Co., Ltd.
+//
+// Authors:
+// Mason Yang 
+// zhengxunli 
+// Boris Brezillon 
+//
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HC_CFG 0x0
+#define HC_CFG_IF_CFG(x)   ((x) << 27)
+#define HC_CFG_DUAL_SLAVE  BIT(31)
+#define HC_CFG_INDIVIDUAL  BIT(30)
+#define HC_CFG_NIO(x)  (((x) / 4) << 27)
+#define HC_CFG_TYPE(s, t)  ((t) << (23 + ((s) * 2)))
+#define HC_CFG_TYPE_SPI_NOR0
+#define HC_CFG_TYPE_SPI_NAND   1
+#define HC_CFG_TYPE_SPI_RAM2
+#define HC_CFG_TYPE_RAW_NAND   3
+#define HC_CFG_SLV_ACT(x)  ((x) << 21)
+#define HC_CFG_CLK_PH_EN   BIT(20)
+#define HC_CFG_CLK_POL_INV BIT(19)
+#define HC_CFG_BIG_ENDIAN  BIT(18)
+#define HC_CFG_DATA_PASS   BIT(17)
+#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
+#define HC_CFG_MAN_START_ENBIT(3)
+#define HC_CFG_MAN_START   BIT(2)
+#define HC_CFG_MAN_CS_EN   BIT(1)
+#define HC_CFG_MAN_CS_ASSERT   BIT(0)
+
+#define INT_STS0x4
+#define INT_STS_EN 0x8
+#define INT_SIG_EN 0xc
+#define INT_STS_ALLGENMASK(31, 0)
+#define INT_RDY_PINBIT(26)
+#define INT_RDY_SR BIT(25)
+#define INT_LNR_SUSP   BIT(24)
+#define INT_ECC_ERRBIT(17)
+#define INT_CRC_ERRBIT(16)
+#define INT_LWR_DISBIT(12)
+#define INT_LRD_DISBIT(11)
+#define INT_SDMA_INT   BIT(10)
+#define INT_DMA_FINISH BIT(9)
+#define INT_RX_NOT_FULLBIT(3)
+#define INT_RX_NOT_EMPTY   BIT(2)
+#define INT_TX_NOT_FULLBIT(1)
+#define INT_TX_EMPTY   BIT(0)
+
+#define HC_EN  0x10
+#define HC_EN_BIT  BIT(0)
+
+#define TXD(x) (0x14 + ((x) * 4))
+#define RXD0x24
+
+#define SS_CTRL(s) (0x30 + ((s) * 4))
+#define LRD_CFG0x44
+#define LWR_CFG0x80
+#define RWW_CFG0x70
+#define OP_READBIT(23)
+#define OP_DUMMY_CYC(x)((x) << 17)
+#define OP_ADDR_BYTES(x)   ((x) << 14)
+#define OP_CMD_BYTES(x)(((x) - 1) << 13)
+#define OP_OCTA_CRC_EN BIT(12)
+#define OP_DQS_EN  BIT(11)
+#define OP_ENHC_EN BIT(10)
+#define OP_PREAMBLE_EN BIT(9)
+#define OP_DATA_DDRBIT(8)
+#define OP_DATA_BUSW(x)((x) << 6)
+#define OP_ADDR_DDRBIT(5)
+#define OP_ADDR_BUSW(x)((x) << 3)
+#define OP_CMD_DDR BIT(2)
+#define OP_CMD_BUSW(x) (x)
+#define OP_BUSW_1  0
+#define OP_BUSW_2  1
+#define OP_BUSW_4  2
+#define OP_BUSW_8  3
+
+#define OCTA_CRC   0x38
+#define OCTA_CRC_IN_EN(s)  BIT(3 + ((s) * 16))
+#define OCTA_CRC_CHUNK(s, x)   ((fls((x) / 32)) << (1 + ((s) * 16)))
+#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
+
+#define ONFI_DIN_CNT(s)(0x3c + (s))
+
+#define LRD_CTRL   0x48
+#define RWW_CTRL   0x74
+#define LWR_CTRL   0x84
+#define LMODE_EN   BIT(31)
+#define LMODE_SLV_ACT(x)   ((x) << 21)