Re: [PATCH v6 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Viresh Kumar]

On 14-05-18, 16:11, Ilia Lin wrote:
> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> that have KRYO processors, the CPU ferequencies subset and voltage value
> of each OPP varies based on the silicon variant in use.
> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
> 
> This change adds documentation.
> 
> Signed-off-by: Ilia Lin 
> ---
>  .../devicetree/bindings/opp/kryo-cpufreq.txt   | 680 
> +
>  1 file changed, 680 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt

Acked-by: Viresh Kumar 

-- 
viresh

Re: [PATCH v6 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Viresh Kumar]

On 14-05-18, 16:11, Ilia Lin wrote:
> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> that have KRYO processors, the CPU ferequencies subset and voltage value
> of each OPP varies based on the silicon variant in use.
> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
> 
> This change adds documentation.
> 
> Signed-off-by: Ilia Lin 
> ---
>  .../devicetree/bindings/opp/kryo-cpufreq.txt   | 680 
> +
>  1 file changed, 680 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt

Acked-by: Viresh Kumar 

-- 
viresh

[PATCH v6 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Ilia Lin]

In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
that have KRYO processors, the CPU ferequencies subset and voltage value
of each OPP varies based on the silicon variant in use.
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
defines the voltage and frequency value based on the msm-id in SMEM
and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.

This change adds documentation.

Signed-off-by: Ilia Lin 
---
 .../devicetree/bindings/opp/kryo-cpufreq.txt   | 680 +
 1 file changed, 680 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt

diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt 
b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
new file mode 100644
index 000..c2127b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
@@ -0,0 +1,680 @@
+Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
+===
+
+In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
+that have KRYO processors, the CPU ferequencies subset and voltage value
+of each OPP varies based on the silicon variant in use.
+Qualcomm Technologies, Inc. Process Voltage Scaling Tables
+defines the voltage and frequency value based on the msm-id in SMEM
+and speedbin blown in the efuse combination.
+The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+to provide the OPP framework with required information (existing HW bitmap).
+This is used to determine the voltage and frequency value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+   - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+   efuse registers that has information about the
+   speedbin that is used to select the right frequency/voltage
+   value pair.
+   Please refer the for nvmem-cells
+   bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+   and also examples below.
+
+In every OPP node:
+- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
+   Bitmap:
+   0:  MSM8996 V3, speedbin 0
+   1:  MSM8996 V3, speedbin 1
+   2:  MSM8996 V3, speedbin 2
+   3:  unused
+   4:  MSM8996 SG, speedbin 0
+   5:  MSM8996 SG, speedbin 1
+   6:  MSM8996 SG, speedbin 2
+   7-31:   unused
+
+Example 1:
+-
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   CPU0: cpu@0 {
+   device_type = "cpu";
+   compatible = "qcom,kryo";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   clocks = < 0>;
+   cpu-supply = <_s11_saw>;
+   operating-points-v2 = <_opp>;
+   #cooling-cells = <2>;
+   next-level-cache = <_0>;
+   L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+   };
+   };
+
+   CPU1: cpu@1 {
+   device_type = "cpu";
+   compatible = "qcom,kryo";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   clocks = < 0>;
+   cpu-supply = <_s11_saw>;
+   operating-points-v2 = <_opp>;
+   #cooling-cells = <2>;
+   next-level-cache = <_0>;
+   };
+
+   CPU2: cpu@100 {
+   device_type = "cpu";
+   compatible = "qcom,kryo";
+   reg = <0x0 0x100>;
+   enable-method = "psci";
+   clocks = < 1>;
+   cpu-supply = <_s11_saw>;
+   operating-points-v2 = <_opp>;
+   #cooling-cells = <2>;
+   next-level-cache = <_1>;
+   L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ 

[PATCH v6 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Ilia Lin]

In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
that have KRYO processors, the CPU ferequencies subset and voltage value
of each OPP varies based on the silicon variant in use.
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
defines the voltage and frequency value based on the msm-id in SMEM
and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.

This change adds documentation.

Signed-off-by: Ilia Lin 
---
 .../devicetree/bindings/opp/kryo-cpufreq.txt   | 680 +
 1 file changed, 680 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt

diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt 
b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
new file mode 100644
index 000..c2127b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
@@ -0,0 +1,680 @@
+Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
+===
+
+In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
+that have KRYO processors, the CPU ferequencies subset and voltage value
+of each OPP varies based on the silicon variant in use.
+Qualcomm Technologies, Inc. Process Voltage Scaling Tables
+defines the voltage and frequency value based on the msm-id in SMEM
+and speedbin blown in the efuse combination.
+The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+to provide the OPP framework with required information (existing HW bitmap).
+This is used to determine the voltage and frequency value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+   - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+   efuse registers that has information about the
+   speedbin that is used to select the right frequency/voltage
+   value pair.
+   Please refer the for nvmem-cells
+   bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+   and also examples below.
+
+In every OPP node:
+- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
+   Bitmap:
+   0:  MSM8996 V3, speedbin 0
+   1:  MSM8996 V3, speedbin 1
+   2:  MSM8996 V3, speedbin 2
+   3:  unused
+   4:  MSM8996 SG, speedbin 0
+   5:  MSM8996 SG, speedbin 1
+   6:  MSM8996 SG, speedbin 2
+   7-31:   unused
+
+Example 1:
+-
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   CPU0: cpu@0 {
+   device_type = "cpu";
+   compatible = "qcom,kryo";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   clocks = < 0>;
+   cpu-supply = <_s11_saw>;
+   operating-points-v2 = <_opp>;
+   #cooling-cells = <2>;
+   next-level-cache = <_0>;
+   L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+   };
+   };
+
+   CPU1: cpu@1 {
+   device_type = "cpu";
+   compatible = "qcom,kryo";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   clocks = < 0>;
+   cpu-supply = <_s11_saw>;
+   operating-points-v2 = <_opp>;
+   #cooling-cells = <2>;
+   next-level-cache = <_0>;
+   };
+
+   CPU2: cpu@100 {
+   device_type = "cpu";
+   compatible = "qcom,kryo";
+   reg = <0x0 0x100>;
+   enable-method = "psci";
+   clocks = < 1>;
+   cpu-supply = <_s11_saw>;
+   operating-points-v2 = <_opp>;
+   #cooling-cells = <2>;
+   next-level-cache = <_1>;
+   L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+   };
+