RE: [PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

2017-11-01 Thread Miodrag Dinic 
Hello Marc,

> > + gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
> > + handle_level_irq);
> > +
> > + ct = gc->chip_types;
> 
> And what if the allocation fails?

Thanks, it will be addressed in V7.

Kind regards,
Miodrag

From: Marc Zyngier [marc.zyng...@arm.com]
Sent: Tuesday, October 31, 2017 3:26 AM
To: Aleksandar Markovic
Cc: linux-m...@linux-mips.org; Miodrag Dinic; Goran Ferenc; Aleksandar 
Markovic; David S. Miller; Douglas Leung; Greg Kroah-Hartman; James Hogan; 
Jason Cooper; linux-kernel@vger.kernel.org; Mauro Carvalho Chehab; Miodrag 
Dinic; Paul Burton; Petar Jovanovic; Raghu Gandham; Randy Dunlap; Thomas 
Gleixner
Subject: Re: [PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

On Mon, Oct 30 2017 at 12:56:33 pm GMT, Aleksandar Markovic 
<aleksandar.marko...@rt-rk.com> wrote:
> From: Miodrag Dinic <miodrag.di...@mips.com>
>
> Add device driver for a virtual programmable interrupt controller
>
> The virtual PIC is designed as a device tree-based interrupt controller.
>
> The compatible string used by OS for binding the driver is
> "google,goldfish-pic".
>
> Signed-off-by: Miodrag Dinic <miodrag.di...@mips.com>
> Signed-off-by: Goran Ferenc <goran.fer...@mips.com>
> Signed-off-by: Aleksandar Markovic <aleksandar.marko...@mips.com>

[...]

> diff --git a/drivers/irqchip/irq-goldfish-pic.c 
> b/drivers/irqchip/irq-goldfish-pic.c
> new file mode 100644
> index 000..48fb773
> --- /dev/null
> +++ b/drivers/irqchip/irq-goldfish-pic.c

[...]

> +static int __init goldfish_pic_of_init(struct device_node *of_node,
> +struct device_node *parent)
> +{
> + struct goldfish_pic_data *gfpic;
> + struct irq_chip_generic *gc;
> + struct irq_chip_type *ct;
> + unsigned int parent_irq;
> + int ret = 0;
> +
> + gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
> + if (!gfpic) {
> + ret = -ENOMEM;
> + goto out_err;
> + }
> +
> + parent_irq = irq_of_parse_and_map(of_node, 0);
> + if (!parent_irq) {
> + pr_err("Failed to map Goldfish PIC parent IRQ\n");
> + ret = -EINVAL;
> + goto out_free;
> + }
> +
> + gfpic->base = of_iomap(of_node, 0);
> + if (!gfpic->base) {
> + pr_err("Failed to map Goldfish PIC base\n");
> + ret = -ENOMEM;
> + goto out_unmap_irq;
> + }
> +
> + /* Mask interrupts. */
> + writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
> +
> + gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
> + handle_level_irq);
> +
> + ct = gc->chip_types;

And what if the allocation fails?

> + ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
> + ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
> + ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
> + ct->chip.irq_mask = irq_gc_mask_disable_reg;
> +
> + irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0, 0,
> +IRQ_NOPROBE | IRQ_LEVEL);
> +
> + gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
> +   GFPIC_IRQ_BASE, 0,
> +   _irq_domain_ops,
> +   NULL);
> + if (!gfpic->irq_domain) {
> + pr_err("Failed to add irqdomain for Goldfish PIC\n");
> + ret = -EINVAL;
> + goto out_iounmap;
> + }
> +
> + irq_set_chained_handler_and_data(parent_irq,
> +  goldfish_pic_cascade, gfpic);
> +
> + pr_info("Successfully registered Goldfish PIC\n");
> + return 0;
> +
> +out_iounmap:
> + iounmap(gfpic->base);
> +out_unmap_irq:
> + irq_dispose_mapping(parent_irq);
> +out_free:
> + kfree(gfpic);
> +out_err:
> + return ret;
> +}
> +
> +IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);

Thanks,

M.
--
Jazz is not dead. It just smells funny.

RE: [PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

2017-11-01 Thread Miodrag Dinic 
Hello Marc,

> > + gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
> > + handle_level_irq);
> > +
> > + ct = gc->chip_types;
> 
> And what if the allocation fails?

Thanks, it will be addressed in V7.

Kind regards,
Miodrag

From: Marc Zyngier [marc.zyng...@arm.com]
Sent: Tuesday, October 31, 2017 3:26 AM
To: Aleksandar Markovic
Cc: linux-m...@linux-mips.org; Miodrag Dinic; Goran Ferenc; Aleksandar 
Markovic; David S. Miller; Douglas Leung; Greg Kroah-Hartman; James Hogan; 
Jason Cooper; linux-kernel@vger.kernel.org; Mauro Carvalho Chehab; Miodrag 
Dinic; Paul Burton; Petar Jovanovic; Raghu Gandham; Randy Dunlap; Thomas 
Gleixner
Subject: Re: [PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

On Mon, Oct 30 2017 at 12:56:33 pm GMT, Aleksandar Markovic 
 wrote:
> From: Miodrag Dinic 
>
> Add device driver for a virtual programmable interrupt controller
>
> The virtual PIC is designed as a device tree-based interrupt controller.
>
> The compatible string used by OS for binding the driver is
> "google,goldfish-pic".
>
> Signed-off-by: Miodrag Dinic 
> Signed-off-by: Goran Ferenc 
> Signed-off-by: Aleksandar Markovic 

[...]

> diff --git a/drivers/irqchip/irq-goldfish-pic.c 
> b/drivers/irqchip/irq-goldfish-pic.c
> new file mode 100644
> index 000..48fb773
> --- /dev/null
> +++ b/drivers/irqchip/irq-goldfish-pic.c

[...]

> +static int __init goldfish_pic_of_init(struct device_node *of_node,
> +struct device_node *parent)
> +{
> + struct goldfish_pic_data *gfpic;
> + struct irq_chip_generic *gc;
> + struct irq_chip_type *ct;
> + unsigned int parent_irq;
> + int ret = 0;
> +
> + gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
> + if (!gfpic) {
> + ret = -ENOMEM;
> + goto out_err;
> + }
> +
> + parent_irq = irq_of_parse_and_map(of_node, 0);
> + if (!parent_irq) {
> + pr_err("Failed to map Goldfish PIC parent IRQ\n");
> + ret = -EINVAL;
> + goto out_free;
> + }
> +
> + gfpic->base = of_iomap(of_node, 0);
> + if (!gfpic->base) {
> + pr_err("Failed to map Goldfish PIC base\n");
> + ret = -ENOMEM;
> + goto out_unmap_irq;
> + }
> +
> + /* Mask interrupts. */
> + writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
> +
> + gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
> + handle_level_irq);
> +
> + ct = gc->chip_types;

And what if the allocation fails?

> + ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
> + ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
> + ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
> + ct->chip.irq_mask = irq_gc_mask_disable_reg;
> +
> + irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0, 0,
> +IRQ_NOPROBE | IRQ_LEVEL);
> +
> + gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
> +   GFPIC_IRQ_BASE, 0,
> +   _irq_domain_ops,
> +   NULL);
> + if (!gfpic->irq_domain) {
> + pr_err("Failed to add irqdomain for Goldfish PIC\n");
> + ret = -EINVAL;
> + goto out_iounmap;
> + }
> +
> + irq_set_chained_handler_and_data(parent_irq,
> +  goldfish_pic_cascade, gfpic);
> +
> + pr_info("Successfully registered Goldfish PIC\n");
> + return 0;
> +
> +out_iounmap:
> + iounmap(gfpic->base);
> +out_unmap_irq:
> + irq_dispose_mapping(parent_irq);
> +out_free:
> + kfree(gfpic);
> +out_err:
> + return ret;
> +}
> +
> +IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);

Thanks,

M.
--
Jazz is not dead. It just smells funny.

Re: [PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

2017-10-30 Thread Marc Zyngier 
On Mon, Oct 30 2017 at 12:56:33 pm GMT, Aleksandar Markovic 
 wrote:
> From: Miodrag Dinic 
>
> Add device driver for a virtual programmable interrupt controller
>
> The virtual PIC is designed as a device tree-based interrupt controller.
>
> The compatible string used by OS for binding the driver is
> "google,goldfish-pic".
>
> Signed-off-by: Miodrag Dinic 
> Signed-off-by: Goran Ferenc 
> Signed-off-by: Aleksandar Markovic 

[...]

> diff --git a/drivers/irqchip/irq-goldfish-pic.c 
> b/drivers/irqchip/irq-goldfish-pic.c
> new file mode 100644
> index 000..48fb773
> --- /dev/null
> +++ b/drivers/irqchip/irq-goldfish-pic.c

[...]

> +static int __init goldfish_pic_of_init(struct device_node *of_node,
> +struct device_node *parent)
> +{
> + struct goldfish_pic_data *gfpic;
> + struct irq_chip_generic *gc;
> + struct irq_chip_type *ct;
> + unsigned int parent_irq;
> + int ret = 0;
> +
> + gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
> + if (!gfpic) {
> + ret = -ENOMEM;
> + goto out_err;
> + }
> +
> + parent_irq = irq_of_parse_and_map(of_node, 0);
> + if (!parent_irq) {
> + pr_err("Failed to map Goldfish PIC parent IRQ\n");
> + ret = -EINVAL;
> + goto out_free;
> + }
> +
> + gfpic->base = of_iomap(of_node, 0);
> + if (!gfpic->base) {
> + pr_err("Failed to map Goldfish PIC base\n");
> + ret = -ENOMEM;
> + goto out_unmap_irq;
> + }
> +
> + /* Mask interrupts. */
> + writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
> +
> + gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
> + handle_level_irq);
> +
> + ct = gc->chip_types;

And what if the allocation fails?

> + ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
> + ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
> + ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
> + ct->chip.irq_mask = irq_gc_mask_disable_reg;
> +
> + irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0, 0,
> +IRQ_NOPROBE | IRQ_LEVEL);
> +
> + gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
> +   GFPIC_IRQ_BASE, 0,
> +   _irq_domain_ops,
> +   NULL);
> + if (!gfpic->irq_domain) {
> + pr_err("Failed to add irqdomain for Goldfish PIC\n");
> + ret = -EINVAL;
> + goto out_iounmap;
> + }
> +
> + irq_set_chained_handler_and_data(parent_irq,
> +  goldfish_pic_cascade, gfpic);
> +
> + pr_info("Successfully registered Goldfish PIC\n");
> + return 0;
> +
> +out_iounmap:
> + iounmap(gfpic->base);
> +out_unmap_irq:
> + irq_dispose_mapping(parent_irq); 
> +out_free:
> + kfree(gfpic);
> +out_err:
> + return ret;
> +}
> +
> +IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);

Thanks,

M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

2017-10-30 Thread Marc Zyngier 
On Mon, Oct 30 2017 at 12:56:33 pm GMT, Aleksandar Markovic 
 wrote:
> From: Miodrag Dinic 
>
> Add device driver for a virtual programmable interrupt controller
>
> The virtual PIC is designed as a device tree-based interrupt controller.
>
> The compatible string used by OS for binding the driver is
> "google,goldfish-pic".
>
> Signed-off-by: Miodrag Dinic 
> Signed-off-by: Goran Ferenc 
> Signed-off-by: Aleksandar Markovic 

[...]

> diff --git a/drivers/irqchip/irq-goldfish-pic.c 
> b/drivers/irqchip/irq-goldfish-pic.c
> new file mode 100644
> index 000..48fb773
> --- /dev/null
> +++ b/drivers/irqchip/irq-goldfish-pic.c

[...]

> +static int __init goldfish_pic_of_init(struct device_node *of_node,
> +struct device_node *parent)
> +{
> + struct goldfish_pic_data *gfpic;
> + struct irq_chip_generic *gc;
> + struct irq_chip_type *ct;
> + unsigned int parent_irq;
> + int ret = 0;
> +
> + gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
> + if (!gfpic) {
> + ret = -ENOMEM;
> + goto out_err;
> + }
> +
> + parent_irq = irq_of_parse_and_map(of_node, 0);
> + if (!parent_irq) {
> + pr_err("Failed to map Goldfish PIC parent IRQ\n");
> + ret = -EINVAL;
> + goto out_free;
> + }
> +
> + gfpic->base = of_iomap(of_node, 0);
> + if (!gfpic->base) {
> + pr_err("Failed to map Goldfish PIC base\n");
> + ret = -ENOMEM;
> + goto out_unmap_irq;
> + }
> +
> + /* Mask interrupts. */
> + writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
> +
> + gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
> + handle_level_irq);
> +
> + ct = gc->chip_types;

And what if the allocation fails?

> + ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
> + ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
> + ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
> + ct->chip.irq_mask = irq_gc_mask_disable_reg;
> +
> + irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0, 0,
> +IRQ_NOPROBE | IRQ_LEVEL);
> +
> + gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
> +   GFPIC_IRQ_BASE, 0,
> +   _irq_domain_ops,
> +   NULL);
> + if (!gfpic->irq_domain) {
> + pr_err("Failed to add irqdomain for Goldfish PIC\n");
> + ret = -EINVAL;
> + goto out_iounmap;
> + }
> +
> + irq_set_chained_handler_and_data(parent_irq,
> +  goldfish_pic_cascade, gfpic);
> +
> + pr_info("Successfully registered Goldfish PIC\n");
> + return 0;
> +
> +out_iounmap:
> + iounmap(gfpic->base);
> +out_unmap_irq:
> + irq_dispose_mapping(parent_irq); 
> +out_free:
> + kfree(gfpic);
> +out_err:
> + return ret;
> +}
> +
> +IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);

Thanks,

M.
-- 
Jazz is not dead. It just smells funny.

[PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

2017-10-30 Thread Aleksandar Markovic 
From: Miodrag Dinic 

Add device driver for a virtual programmable interrupt controller

The virtual PIC is designed as a device tree-based interrupt controller.

The compatible string used by OS for binding the driver is
"google,goldfish-pic".

Signed-off-by: Miodrag Dinic 
Signed-off-by: Goran Ferenc 
Signed-off-by: Aleksandar Markovic 
---
 MAINTAINERS|   1 +
 drivers/irqchip/Kconfig|   8 +++
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-goldfish-pic.c | 128 +
 4 files changed, 138 insertions(+)
 create mode 100644 drivers/irqchip/irq-goldfish-pic.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 4d5108f..f1be016 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -876,6 +876,7 @@ ANDROID GOLDFISH PIC DRIVER
 M: Miodrag Dinic 
 S: Supported
 F: 
Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
+F: drivers/irqchip/irq-goldfish-pic.c
 
 ANDROID GOLDFISH RTC DRIVER
 M: Miodrag Dinic 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 9d8a1dd..712b561 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -321,3 +321,11 @@ config IRQ_UNIPHIER_AIDET
select IRQ_DOMAIN_HIERARCHY
help
  Support for the UniPhier AIDET (ARM Interrupt Detector).
+
+config GOLDFISH_PIC
+   bool "Goldfish programmable interrupt controller"
+   depends on MIPS && (GOLDFISH || COMPILE_TEST)
+   select IRQ_DOMAIN
+   help
+ Say yes here to enable Goldfish interrupt controller driver used
+ for Goldfish based virtual platforms.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 845abc1..0e7a224 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -79,3 +79,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o 
irq-aspeed-i2c-ic.o
 obj-$(CONFIG_STM32_EXTI)   += irq-stm32-exti.o
 obj-$(CONFIG_QCOM_IRQ_COMBINER)+= qcom-irq-combiner.o
 obj-$(CONFIG_IRQ_UNIPHIER_AIDET)   += irq-uniphier-aidet.o
+obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
diff --git a/drivers/irqchip/irq-goldfish-pic.c 
b/drivers/irqchip/irq-goldfish-pic.c
new file mode 100644
index 000..48fb773
--- /dev/null
+++ b/drivers/irqchip/irq-goldfish-pic.c
@@ -0,0 +1,128 @@
+/*
+ * Driver for MIPS Goldfish Programmable Interrupt Controller.
+ *
+ * Author: Miodrag Dinic 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define GFPIC_NR_IRQS  32
+
+/* 8..39 Cascaded Goldfish PIC interrupts */
+#define GFPIC_IRQ_BASE 8
+
+#define GFPIC_REG_IRQ_PENDING  0x04
+#define GFPIC_REG_IRQ_DISABLE_ALL  0x08
+#define GFPIC_REG_IRQ_DISABLE  0x0c
+#define GFPIC_REG_IRQ_ENABLE   0x10
+
+struct goldfish_pic_data {
+   void __iomem *base;
+   struct irq_domain *irq_domain;
+};
+
+static void goldfish_pic_cascade(struct irq_desc *desc)
+{
+   struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
+   struct irq_chip *host_chip = irq_desc_get_chip(desc);
+   u32 pending, hwirq, virq;
+
+   chained_irq_enter(host_chip, desc);
+
+   pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
+   while (pending) {
+   hwirq = __fls(pending);
+   virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
+   generic_handle_irq(virq);
+   pending &= ~(1 << hwirq);
+   }
+
+   chained_irq_exit(host_chip, desc);
+}
+
+static const struct irq_domain_ops goldfish_irq_domain_ops = {
+   .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init goldfish_pic_of_init(struct device_node *of_node,
+  struct device_node *parent)
+{
+   struct goldfish_pic_data *gfpic;
+   struct irq_chip_generic *gc;
+   struct irq_chip_type *ct;
+   unsigned int parent_irq;
+   int ret = 0;
+
+   gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
+   if (!gfpic) {
+   ret = -ENOMEM;
+   goto out_err;
+   }
+
+   parent_irq = irq_of_parse_and_map(of_node, 0);
+   if (!parent_irq) {
+   pr_err("Failed to map Goldfish PIC parent IRQ\n");
+   ret = -EINVAL;
+   goto out_free;
+   }
+
+   gfpic->base = of_iomap(of_node, 0);
+   if (!gfpic->base) {
+   pr_err("Failed to map Goldfish PIC base\n");
+   ret = -ENOMEM;
+   goto

[PATCH v6 2/5] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

2017-10-30 Thread Aleksandar Markovic 
From: Miodrag Dinic 

Add device driver for a virtual programmable interrupt controller

The virtual PIC is designed as a device tree-based interrupt controller.

The compatible string used by OS for binding the driver is
"google,goldfish-pic".

Signed-off-by: Miodrag Dinic 
Signed-off-by: Goran Ferenc 
Signed-off-by: Aleksandar Markovic 
---
 MAINTAINERS|   1 +
 drivers/irqchip/Kconfig|   8 +++
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-goldfish-pic.c | 128 +
 4 files changed, 138 insertions(+)
 create mode 100644 drivers/irqchip/irq-goldfish-pic.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 4d5108f..f1be016 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -876,6 +876,7 @@ ANDROID GOLDFISH PIC DRIVER
 M: Miodrag Dinic 
 S: Supported
 F: 
Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
+F: drivers/irqchip/irq-goldfish-pic.c
 
 ANDROID GOLDFISH RTC DRIVER
 M: Miodrag Dinic 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 9d8a1dd..712b561 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -321,3 +321,11 @@ config IRQ_UNIPHIER_AIDET
select IRQ_DOMAIN_HIERARCHY
help
  Support for the UniPhier AIDET (ARM Interrupt Detector).
+
+config GOLDFISH_PIC
+   bool "Goldfish programmable interrupt controller"
+   depends on MIPS && (GOLDFISH || COMPILE_TEST)
+   select IRQ_DOMAIN
+   help
+ Say yes here to enable Goldfish interrupt controller driver used
+ for Goldfish based virtual platforms.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 845abc1..0e7a224 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -79,3 +79,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o 
irq-aspeed-i2c-ic.o
 obj-$(CONFIG_STM32_EXTI)   += irq-stm32-exti.o
 obj-$(CONFIG_QCOM_IRQ_COMBINER)+= qcom-irq-combiner.o
 obj-$(CONFIG_IRQ_UNIPHIER_AIDET)   += irq-uniphier-aidet.o
+obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
diff --git a/drivers/irqchip/irq-goldfish-pic.c 
b/drivers/irqchip/irq-goldfish-pic.c
new file mode 100644
index 000..48fb773
--- /dev/null
+++ b/drivers/irqchip/irq-goldfish-pic.c
@@ -0,0 +1,128 @@
+/*
+ * Driver for MIPS Goldfish Programmable Interrupt Controller.
+ *
+ * Author: Miodrag Dinic 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define GFPIC_NR_IRQS  32
+
+/* 8..39 Cascaded Goldfish PIC interrupts */
+#define GFPIC_IRQ_BASE 8
+
+#define GFPIC_REG_IRQ_PENDING  0x04
+#define GFPIC_REG_IRQ_DISABLE_ALL  0x08
+#define GFPIC_REG_IRQ_DISABLE  0x0c
+#define GFPIC_REG_IRQ_ENABLE   0x10
+
+struct goldfish_pic_data {
+   void __iomem *base;
+   struct irq_domain *irq_domain;
+};
+
+static void goldfish_pic_cascade(struct irq_desc *desc)
+{
+   struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
+   struct irq_chip *host_chip = irq_desc_get_chip(desc);
+   u32 pending, hwirq, virq;
+
+   chained_irq_enter(host_chip, desc);
+
+   pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
+   while (pending) {
+   hwirq = __fls(pending);
+   virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
+   generic_handle_irq(virq);
+   pending &= ~(1 << hwirq);
+   }
+
+   chained_irq_exit(host_chip, desc);
+}
+
+static const struct irq_domain_ops goldfish_irq_domain_ops = {
+   .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init goldfish_pic_of_init(struct device_node *of_node,
+  struct device_node *parent)
+{
+   struct goldfish_pic_data *gfpic;
+   struct irq_chip_generic *gc;
+   struct irq_chip_type *ct;
+   unsigned int parent_irq;
+   int ret = 0;
+
+   gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
+   if (!gfpic) {
+   ret = -ENOMEM;
+   goto out_err;
+   }
+
+   parent_irq = irq_of_parse_and_map(of_node, 0);
+   if (!parent_irq) {
+   pr_err("Failed to map Goldfish PIC parent IRQ\n");
+   ret = -EINVAL;
+   goto out_free;
+   }
+
+   gfpic->base = of_iomap(of_node, 0);
+   if (!gfpic->base) {
+   pr_err("Failed to map Goldfish PIC base\n");
+   ret = -ENOMEM;
+   goto out_unmap_irq;
+   }
+
+   /* Mask interrupts. */
+   writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
+
+   gc = irq_alloc_generic_chip("GFPIC", 1,