Re: [PATCH v6 4/5] phy: rockchip-typec: support variable phy config value

[Enric Balletbo Serra]

Hi Lin,

2018-05-21 11:37 GMT+02:00 Lin Huang :
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
>
> Signed-off-by: Chris Zhong 
> Signed-off-by: Lin Huang 
> ---
> Changes in v2:
> - update patch following Enric suggest
> Changes in v3:
> - delete need_software_training variable
> - add default phy config value, if dts do not define phy config value, use 
> these value
> Changes in v4:
> - rename variable config to tcphy_default_config
> Changes in v5:
> - None
> Changes in v6:
> - split the header file to new patch
>
>  drivers/phy/rockchip/phy-rockchip-typec.c | 261 
> --
>  1 file changed, 208 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
> b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 795055f..4c4b925 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -324,21 +324,29 @@
>   * clock 0: PLL 0 div 1
>   * clock 1: PLL 1 div 2
>   */
> -#define CLK_PLL_CONFIG 0X30
> +#define CLK_PLL1_DIV1  0x20
> +#define CLK_PLL1_DIV2  0x30
>  #define CLK_PLL_MASK   0x33
>
>  #define CMN_READY  BIT(0)
>
> +#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
>  #define DP_PLL_CLOCK_ENABLEBIT(2)
> +#define DP_PLL_ENABLE_ACK  BIT(1)
>  #define DP_PLL_ENABLE  BIT(0)
>  #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
> +#define DP_PLL_DATA_RATE_MASK  0xff00
>
> -#define DP_MODE_A0 BIT(4)
> -#define DP_MODE_A2 BIT(6)
> -#define DP_MODE_ENTER_A0   0xc101
> -#define DP_MODE_ENTER_A2   0xc104
> +#define DP_MODE_MASK   0xf
> +#define DP_MODE_ENTER_A0   BIT(0)
> +#define DP_MODE_ENTER_A2   BIT(2)
> +#define DP_MODE_ENTER_A3   BIT(3)
> +#define DP_MODE_A0_ACK BIT(4)
> +#define DP_MODE_A2_ACK BIT(6)
> +#define DP_MODE_A3_ACK BIT(7)
> +#define DP_LINK_RESET_DEASSERTED   BIT(8)
>
>  #define PHY_MODE_SET_TIMEOUT   10
>
> @@ -350,6 +358,8 @@
>  #define MODE_DFP_USB   BIT(1)
>  #define MODE_DFP_DPBIT(2)
>
> +#define DP_DEFAULT_RATE162000
> +
>  struct phy_reg {
> u16 value;
> u32 addr;
> @@ -372,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
> { 0x8,  CMN_DIAG_PLL0_LF_PROG },
>  };
>
> -struct phy_reg dp_pll_cfg[] = {
> +struct phy_reg dp_pll_rbr_cfg[] = {
> { 0xf0, CMN_PLL1_VCOCAL_INIT },
> { 0x18, CMN_PLL1_VCOCAL_ITER },
> { 0x30b9,   CMN_PLL1_VCOCAL_START },
> -   { 0x21c,CMN_PLL1_INTDIV },
> +   { 0x87, CMN_PLL1_INTDIV },
> { 0,CMN_PLL1_FRACDIV },
> -   { 0x5,  CMN_PLL1_HIGH_THR },
> -   { 0x35, CMN_PLL1_SS_CTRL1 },
> -   { 0x7f1e,   CMN_PLL1_SS_CTRL2 },
> +   { 0x22, CMN_PLL1_HIGH_THR },
> +   { 0x8000,   CMN_PLL1_SS_CTRL1 },
> +   { 0,CMN_PLL1_SS_CTRL2 },
> { 0x20, CMN_PLL1_DSM_DIAG },
> { 0,CMN_PLLSM1_USER_DEF_CTRL },
> { 0,CMN_DIAG_PLL1_OVRD },
> @@ -391,9 +401,52 @@ struct phy_reg dp_pll_cfg[] = {
> { 0x8,  CMN_DIAG_PLL1_LF_PROG },
> { 0x100,CMN_DIAG_PLL1_PTATIS_TUNE1 },
> { 0x7,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
> -   { 0x4,  CMN_DIAG_PLL1_INCLK_CTRL },
> +   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
>  };
>
> +struct phy_reg dp_pll_hbr_cfg[] = {
> +   { 0xf0, CMN_PLL1_VCOCAL_INIT },
> +   { 0x18, CMN_PLL1_VCOCAL_ITER },
> +   { 0x30b4,   CMN_PLL1_VCOCAL_START },
> +   { 0xe1, CMN_PLL1_INTDIV },
> +   { 0,CMN_PLL1_FRACDIV },
> +   { 0x5,  CMN_PLL1_HIGH_THR },
> +   { 0x8000,   CMN_PLL1_SS_CTRL1 },
> +   { 0,CMN_PLL1_SS_CTRL2 },
> +   { 0x20, CMN_PLL1_DSM_DIAG },
> +   { 0x1000,   CMN_PLLSM1_USER_DEF_CTRL },
> +   { 0,CMN_DIAG_PLL1_OVRD },
> +   { 0,CMN_DIAG_PLL1_FBH_OVRD },
> +   { 0,CMN_DIAG_PLL1_FBL_OVRD },
> +   { 0x7,  CMN_DIAG_PLL1_V2I_TUNE },
> +   { 0x45, CMN_DIAG_PLL1_CP_TUNE },
> +   { 0x8,  CMN_DIAG_PLL1_LF_PROG },
> +   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE1 },
> +   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
> +   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
> +};
> +
> 

Re: [PATCH v6 4/5] phy: rockchip-typec: support variable phy config value

[Enric Balletbo Serra]

Hi Lin,

2018-05-21 11:37 GMT+02:00 Lin Huang :
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
>
> Signed-off-by: Chris Zhong 
> Signed-off-by: Lin Huang 
> ---
> Changes in v2:
> - update patch following Enric suggest
> Changes in v3:
> - delete need_software_training variable
> - add default phy config value, if dts do not define phy config value, use 
> these value
> Changes in v4:
> - rename variable config to tcphy_default_config
> Changes in v5:
> - None
> Changes in v6:
> - split the header file to new patch
>
>  drivers/phy/rockchip/phy-rockchip-typec.c | 261 
> --
>  1 file changed, 208 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
> b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 795055f..4c4b925 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -324,21 +324,29 @@
>   * clock 0: PLL 0 div 1
>   * clock 1: PLL 1 div 2
>   */
> -#define CLK_PLL_CONFIG 0X30
> +#define CLK_PLL1_DIV1  0x20
> +#define CLK_PLL1_DIV2  0x30
>  #define CLK_PLL_MASK   0x33
>
>  #define CMN_READY  BIT(0)
>
> +#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
>  #define DP_PLL_CLOCK_ENABLEBIT(2)
> +#define DP_PLL_ENABLE_ACK  BIT(1)
>  #define DP_PLL_ENABLE  BIT(0)
>  #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
> +#define DP_PLL_DATA_RATE_MASK  0xff00
>
> -#define DP_MODE_A0 BIT(4)
> -#define DP_MODE_A2 BIT(6)
> -#define DP_MODE_ENTER_A0   0xc101
> -#define DP_MODE_ENTER_A2   0xc104
> +#define DP_MODE_MASK   0xf
> +#define DP_MODE_ENTER_A0   BIT(0)
> +#define DP_MODE_ENTER_A2   BIT(2)
> +#define DP_MODE_ENTER_A3   BIT(3)
> +#define DP_MODE_A0_ACK BIT(4)
> +#define DP_MODE_A2_ACK BIT(6)
> +#define DP_MODE_A3_ACK BIT(7)
> +#define DP_LINK_RESET_DEASSERTED   BIT(8)
>
>  #define PHY_MODE_SET_TIMEOUT   10
>
> @@ -350,6 +358,8 @@
>  #define MODE_DFP_USB   BIT(1)
>  #define MODE_DFP_DPBIT(2)
>
> +#define DP_DEFAULT_RATE162000
> +
>  struct phy_reg {
> u16 value;
> u32 addr;
> @@ -372,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
> { 0x8,  CMN_DIAG_PLL0_LF_PROG },
>  };
>
> -struct phy_reg dp_pll_cfg[] = {
> +struct phy_reg dp_pll_rbr_cfg[] = {
> { 0xf0, CMN_PLL1_VCOCAL_INIT },
> { 0x18, CMN_PLL1_VCOCAL_ITER },
> { 0x30b9,   CMN_PLL1_VCOCAL_START },
> -   { 0x21c,CMN_PLL1_INTDIV },
> +   { 0x87, CMN_PLL1_INTDIV },
> { 0,CMN_PLL1_FRACDIV },
> -   { 0x5,  CMN_PLL1_HIGH_THR },
> -   { 0x35, CMN_PLL1_SS_CTRL1 },
> -   { 0x7f1e,   CMN_PLL1_SS_CTRL2 },
> +   { 0x22, CMN_PLL1_HIGH_THR },
> +   { 0x8000,   CMN_PLL1_SS_CTRL1 },
> +   { 0,CMN_PLL1_SS_CTRL2 },
> { 0x20, CMN_PLL1_DSM_DIAG },
> { 0,CMN_PLLSM1_USER_DEF_CTRL },
> { 0,CMN_DIAG_PLL1_OVRD },
> @@ -391,9 +401,52 @@ struct phy_reg dp_pll_cfg[] = {
> { 0x8,  CMN_DIAG_PLL1_LF_PROG },
> { 0x100,CMN_DIAG_PLL1_PTATIS_TUNE1 },
> { 0x7,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
> -   { 0x4,  CMN_DIAG_PLL1_INCLK_CTRL },
> +   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
>  };
>
> +struct phy_reg dp_pll_hbr_cfg[] = {
> +   { 0xf0, CMN_PLL1_VCOCAL_INIT },
> +   { 0x18, CMN_PLL1_VCOCAL_ITER },
> +   { 0x30b4,   CMN_PLL1_VCOCAL_START },
> +   { 0xe1, CMN_PLL1_INTDIV },
> +   { 0,CMN_PLL1_FRACDIV },
> +   { 0x5,  CMN_PLL1_HIGH_THR },
> +   { 0x8000,   CMN_PLL1_SS_CTRL1 },
> +   { 0,CMN_PLL1_SS_CTRL2 },
> +   { 0x20, CMN_PLL1_DSM_DIAG },
> +   { 0x1000,   CMN_PLLSM1_USER_DEF_CTRL },
> +   { 0,CMN_DIAG_PLL1_OVRD },
> +   { 0,CMN_DIAG_PLL1_FBH_OVRD },
> +   { 0,CMN_DIAG_PLL1_FBL_OVRD },
> +   { 0x7,  CMN_DIAG_PLL1_V2I_TUNE },
> +   { 0x45, CMN_DIAG_PLL1_CP_TUNE },
> +   { 0x8,  CMN_DIAG_PLL1_LF_PROG },
> +   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE1 },
> +   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
> +   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
> +};
> +
> +struct phy_reg dp_pll_hbr2_cfg[] = {
> +   { 0xf0, 

[PATCH v6 4/5] phy: rockchip-typec: support variable phy config value

[Lin Huang]

the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.

Signed-off-by: Chris Zhong 
Signed-off-by: Lin Huang 
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- delete need_software_training variable
- add default phy config value, if dts do not define phy config value, use 
these value
Changes in v4:
- rename variable config to tcphy_default_config
Changes in v5:
- None
Changes in v6:
- split the header file to new patch

 drivers/phy/rockchip/phy-rockchip-typec.c | 261 --
 1 file changed, 208 insertions(+), 53 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
b/drivers/phy/rockchip/phy-rockchip-typec.c
index 795055f..4c4b925 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -324,21 +324,29 @@
  * clock 0: PLL 0 div 1
  * clock 1: PLL 1 div 2
  */
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1  0x20
+#define CLK_PLL1_DIV2  0x30
 #define CLK_PLL_MASK   0x33
 
 #define CMN_READY  BIT(0)
 
+#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
 #define DP_PLL_CLOCK_ENABLEBIT(2)
+#define DP_PLL_ENABLE_ACK  BIT(1)
 #define DP_PLL_ENABLE  BIT(0)
 #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK  0xff00
 
-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0   0xc101
-#define DP_MODE_ENTER_A2   0xc104
+#define DP_MODE_MASK   0xf
+#define DP_MODE_ENTER_A0   BIT(0)
+#define DP_MODE_ENTER_A2   BIT(2)
+#define DP_MODE_ENTER_A3   BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED   BIT(8)
 
 #define PHY_MODE_SET_TIMEOUT   10
 
@@ -350,6 +358,8 @@
 #define MODE_DFP_USB   BIT(1)
 #define MODE_DFP_DPBIT(2)
 
+#define DP_DEFAULT_RATE162000
+
 struct phy_reg {
u16 value;
u32 addr;
@@ -372,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
{ 0x8,  CMN_DIAG_PLL0_LF_PROG },
 };
 
-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b9,   CMN_PLL1_VCOCAL_START },
-   { 0x21c,CMN_PLL1_INTDIV },
+   { 0x87, CMN_PLL1_INTDIV },
{ 0,CMN_PLL1_FRACDIV },
-   { 0x5,  CMN_PLL1_HIGH_THR },
-   { 0x35, CMN_PLL1_SS_CTRL1 },
-   { 0x7f1e,   CMN_PLL1_SS_CTRL2 },
+   { 0x22, CMN_PLL1_HIGH_THR },
+   { 0x8000,   CMN_PLL1_SS_CTRL1 },
+   { 0,CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0,CMN_PLLSM1_USER_DEF_CTRL },
{ 0,CMN_DIAG_PLL1_OVRD },
@@ -391,9 +401,52 @@ struct phy_reg dp_pll_cfg[] = {
{ 0x8,  CMN_DIAG_PLL1_LF_PROG },
{ 0x100,CMN_DIAG_PLL1_PTATIS_TUNE1 },
{ 0x7,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
-   { 0x4,  CMN_DIAG_PLL1_INCLK_CTRL },
+   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
 };
 
+struct phy_reg dp_pll_hbr_cfg[] = {
+   { 0xf0, CMN_PLL1_VCOCAL_INIT },
+   { 0x18, CMN_PLL1_VCOCAL_ITER },
+   { 0x30b4,   CMN_PLL1_VCOCAL_START },
+   { 0xe1, CMN_PLL1_INTDIV },
+   { 0,CMN_PLL1_FRACDIV },
+   { 0x5,  CMN_PLL1_HIGH_THR },
+   { 0x8000,   CMN_PLL1_SS_CTRL1 },
+   { 0,CMN_PLL1_SS_CTRL2 },
+   { 0x20, CMN_PLL1_DSM_DIAG },
+   { 0x1000,   CMN_PLLSM1_USER_DEF_CTRL },
+   { 0,CMN_DIAG_PLL1_OVRD },
+   { 0,CMN_DIAG_PLL1_FBH_OVRD },
+   { 0,CMN_DIAG_PLL1_FBL_OVRD },
+   { 0x7,  CMN_DIAG_PLL1_V2I_TUNE },
+   { 0x45, CMN_DIAG_PLL1_CP_TUNE },
+   { 0x8,  CMN_DIAG_PLL1_LF_PROG },
+   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE1 },
+   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
+   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
+};
+
+struct phy_reg dp_pll_hbr2_cfg[] = {
+   { 0xf0, CMN_PLL1_VCOCAL_INIT },
+   { 0x18, CMN_PLL1_VCOCAL_ITER },
+   { 0x30b4,   CMN_PLL1_VCOCAL_START },
+   { 0xe1, CMN_PLL1_INTDIV },
+   { 0,CMN_PLL1_FRACDIV },
+   { 0x5,  

[PATCH v6 4/5] phy: rockchip-typec: support variable phy config value

[Lin Huang]

the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.

Signed-off-by: Chris Zhong 
Signed-off-by: Lin Huang 
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- delete need_software_training variable
- add default phy config value, if dts do not define phy config value, use 
these value
Changes in v4:
- rename variable config to tcphy_default_config
Changes in v5:
- None
Changes in v6:
- split the header file to new patch

 drivers/phy/rockchip/phy-rockchip-typec.c | 261 --
 1 file changed, 208 insertions(+), 53 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
b/drivers/phy/rockchip/phy-rockchip-typec.c
index 795055f..4c4b925 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -324,21 +324,29 @@
  * clock 0: PLL 0 div 1
  * clock 1: PLL 1 div 2
  */
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1  0x20
+#define CLK_PLL1_DIV2  0x30
 #define CLK_PLL_MASK   0x33
 
 #define CMN_READY  BIT(0)
 
+#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
 #define DP_PLL_CLOCK_ENABLEBIT(2)
+#define DP_PLL_ENABLE_ACK  BIT(1)
 #define DP_PLL_ENABLE  BIT(0)
 #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK  0xff00
 
-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0   0xc101
-#define DP_MODE_ENTER_A2   0xc104
+#define DP_MODE_MASK   0xf
+#define DP_MODE_ENTER_A0   BIT(0)
+#define DP_MODE_ENTER_A2   BIT(2)
+#define DP_MODE_ENTER_A3   BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED   BIT(8)
 
 #define PHY_MODE_SET_TIMEOUT   10
 
@@ -350,6 +358,8 @@
 #define MODE_DFP_USB   BIT(1)
 #define MODE_DFP_DPBIT(2)
 
+#define DP_DEFAULT_RATE162000
+
 struct phy_reg {
u16 value;
u32 addr;
@@ -372,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
{ 0x8,  CMN_DIAG_PLL0_LF_PROG },
 };
 
-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b9,   CMN_PLL1_VCOCAL_START },
-   { 0x21c,CMN_PLL1_INTDIV },
+   { 0x87, CMN_PLL1_INTDIV },
{ 0,CMN_PLL1_FRACDIV },
-   { 0x5,  CMN_PLL1_HIGH_THR },
-   { 0x35, CMN_PLL1_SS_CTRL1 },
-   { 0x7f1e,   CMN_PLL1_SS_CTRL2 },
+   { 0x22, CMN_PLL1_HIGH_THR },
+   { 0x8000,   CMN_PLL1_SS_CTRL1 },
+   { 0,CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0,CMN_PLLSM1_USER_DEF_CTRL },
{ 0,CMN_DIAG_PLL1_OVRD },
@@ -391,9 +401,52 @@ struct phy_reg dp_pll_cfg[] = {
{ 0x8,  CMN_DIAG_PLL1_LF_PROG },
{ 0x100,CMN_DIAG_PLL1_PTATIS_TUNE1 },
{ 0x7,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
-   { 0x4,  CMN_DIAG_PLL1_INCLK_CTRL },
+   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
 };
 
+struct phy_reg dp_pll_hbr_cfg[] = {
+   { 0xf0, CMN_PLL1_VCOCAL_INIT },
+   { 0x18, CMN_PLL1_VCOCAL_ITER },
+   { 0x30b4,   CMN_PLL1_VCOCAL_START },
+   { 0xe1, CMN_PLL1_INTDIV },
+   { 0,CMN_PLL1_FRACDIV },
+   { 0x5,  CMN_PLL1_HIGH_THR },
+   { 0x8000,   CMN_PLL1_SS_CTRL1 },
+   { 0,CMN_PLL1_SS_CTRL2 },
+   { 0x20, CMN_PLL1_DSM_DIAG },
+   { 0x1000,   CMN_PLLSM1_USER_DEF_CTRL },
+   { 0,CMN_DIAG_PLL1_OVRD },
+   { 0,CMN_DIAG_PLL1_FBH_OVRD },
+   { 0,CMN_DIAG_PLL1_FBL_OVRD },
+   { 0x7,  CMN_DIAG_PLL1_V2I_TUNE },
+   { 0x45, CMN_DIAG_PLL1_CP_TUNE },
+   { 0x8,  CMN_DIAG_PLL1_LF_PROG },
+   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE1 },
+   { 0x1,  CMN_DIAG_PLL1_PTATIS_TUNE2 },
+   { 0x1,  CMN_DIAG_PLL1_INCLK_CTRL },
+};
+
+struct phy_reg dp_pll_hbr2_cfg[] = {
+   { 0xf0, CMN_PLL1_VCOCAL_INIT },
+   { 0x18, CMN_PLL1_VCOCAL_ITER },
+   { 0x30b4,   CMN_PLL1_VCOCAL_START },
+   { 0xe1, CMN_PLL1_INTDIV },
+   { 0,CMN_PLL1_FRACDIV },
+   { 0x5,  CMN_PLL1_HIGH_THR },
+   { 0x8000,