Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas wrote: > On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote: >> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP >> >> Signed-off-by: Srikanth Thokala >> Acked-by: Arnd Bergmann > > Applied to pci/host-xilinx for v3.18, thanks! Thanks Bjorn! Srikanth > >> --- >> Changes in v7: >> - Removed errors reported from build-bot. The errors are >> mainly due to same CONFIG_PCI_XILINX flag being used for >> Zynq and Microblaze platforms. So, renamed the driver >> config flag name to CONFIG_PCIE_XILINX. >> - Also, renamed the driver file to pcie-xilinx.c to be in >> sync with CONFIG option. >> - Fixed the annotation of xilinx_pcie_scan_bus() function >> to remove build-bot warnings. >> >> Changes in v6: >> - Added Ack from Arnd. Thanks Arnd. >> - Rebased on 3.16-rc7. >> >> Changes in v5: >> - Removed unnecessary checking of port structure. >> - Changed the return type of verify_config from int to bool. >> - Renamed following functions, >> xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() >> xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() >> xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() >> - Removed link_up bool flag from port structure, as it is not >> being used. >> - Removed unused constants. >> - Rebased on 3.16-rc6. >> - Fixed some minor comments. >> - Thanks Bjorn for the review. >> >> Changes in v4: >> - Regarding the comments to separate ECAM functionality, >> I have sent a separate patch and it is decided to implement >> it later. The patch is here, >> https://lkml.org/lkml/2014/5/18/54 >> - Fixed issue with adding configuration bus resource. >> - Moved the logic for setting up bus resources to probe() from >> pcie_setup(). >> - Instead of mapping all the MSI interrupts in the probe, changed >> to map only when a MSI is requested. >> - Earlier, the implementation of legacy and MSI interrupts init- >> is mutually exclusive, now changed to have the legacy interrupts >> init always and MSI interrupt init based on CONFIG_PCI_MSI flag. >> - Regarding the MSI generic implementation comment, I will plan to >> do on top of this driver patch. >> - Rebased on 3.16-rc2. >> - Fixed other minor comments. >> - Thanks Arnd and Bjorn for the review. >> >> Changes in v3: >> - Rebased on v3.15.0-rc1 >> - Added support for interrupt-map DT functionality. >> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). >> - Modified resource mapping logic as per the series >> "PCI: ARM: add support for generic PCI host controller" >> - Modified devicetree binding documentation to update with interrupt- >> map properties. >> - Use devm calls wherever applicable. >> - Fixed minor comments from Jason >> - Thanks Jason for the review and suggestions. >> >> Changes in v2: >> - Rebased on v3.14.0-rc8 >> - Removed IP specific DT properties like include-rc, axibar-num etc., >> as suggested by Jason and Bjorn, Thanks >> --- >> .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ >> drivers/pci/host/Kconfig |7 + >> drivers/pci/host/Makefile |1 + >> drivers/pci/host/pcie-xilinx.c | 978 >> >> 4 files changed, 1048 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> create mode 100644 drivers/pci/host/pcie-xilinx.c >> >> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> new file mode 100644 >> index 000..3e2c88d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> @@ -0,0 +1,62 @@ >> +* Xilinx AXI PCIe Root Port Bridge DT description >> + >> +Required properties: >> +- #address-cells: Address representation for root ports, set to <3> >> +- #size-cells: Size representation for root ports, set to <2> >> +- #interrupt-cells: specifies the number of cells needed to encode an >> + interrupt source. The value must be 1. >> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" >> +- reg: Should contain AXI PCIe registers location and length >> +- device_type: must be "pci" >> +- interrupts: Should contain AXI PCIe interrupt >> +- interrupt-map-mask, >> + interrupt-map: standard PCI properties to define the mapping of the >> + PCI interface to interrupt numbers. >> +- ranges: ranges for the PCI memory regions (I/O space region is not >> + supported by hardware) >> + Please refer to the standard PCI bus binding document for a more >> + detailed explanation >> + >> +Optional properties: >> +- bus-range: PCI bus numbers covered >> + >> +Interrupt controller child node >> >> +Required properties: >> +- interrupt-controller: identifies the node as an interrupt controller >> +- #address-cells: specifies the number of cells needed to encode an >> + address. The value must be
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas bhelg...@google.com wrote: On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote: This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala stho...@xilinx.com Acked-by: Arnd Bergmann a...@arndb.de Applied to pci/host-xilinx for v3.18, thanks! Thanks Bjorn! Srikanth --- Changes in v7: - Removed errors reported from build-bot. The errors are mainly due to same CONFIG_PCI_XILINX flag being used for Zynq and Microblaze platforms. So, renamed the driver config flag name to CONFIG_PCIE_XILINX. - Also, renamed the driver file to pcie-xilinx.c to be in sync with CONFIG option. - Fixed the annotation of xilinx_pcie_scan_bus() function to remove build-bot warnings. Changes in v6: - Added Ack from Arnd. Thanks Arnd. - Rebased on 3.16-rc7. Changes in v5: - Removed unnecessary checking of port structure. - Changed the return type of verify_config from int to bool. - Renamed following functions, xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up() xilinx_pcie_verify_config() - xilinx_pcie_valid_device() xilinx_pcie_get_config_base() - xilinx_pcie_config_base() - Removed link_up bool flag from port structure, as it is not being used. - Removed unused constants. - Rebased on 3.16-rc6. - Fixed some minor comments. - Thanks Bjorn for the review. Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series PCI: ARM: add support for generic PCI host controller - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-xilinx.c | 978 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pcie-xilinx.c diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to 3 +- #size-cells: Size representation for root ports, set to 2 +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain xlnx,axi-pcie-host-1.00.a +- reg: Should contain AXI PCIe registers location and length +- device_type: must be pci +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote: > This is the driver for Xilinx AXI PCIe Host Bridge Soft IP > > Signed-off-by: Srikanth Thokala > Acked-by: Arnd Bergmann Applied to pci/host-xilinx for v3.18, thanks! > --- > Changes in v7: > - Removed errors reported from build-bot. The errors are > mainly due to same CONFIG_PCI_XILINX flag being used for > Zynq and Microblaze platforms. So, renamed the driver > config flag name to CONFIG_PCIE_XILINX. > - Also, renamed the driver file to pcie-xilinx.c to be in > sync with CONFIG option. > - Fixed the annotation of xilinx_pcie_scan_bus() function > to remove build-bot warnings. > > Changes in v6: > - Added Ack from Arnd. Thanks Arnd. > - Rebased on 3.16-rc7. > > Changes in v5: > - Removed unnecessary checking of port structure. > - Changed the return type of verify_config from int to bool. > - Renamed following functions, > xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() > xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() > xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() > - Removed link_up bool flag from port structure, as it is not > being used. > - Removed unused constants. > - Rebased on 3.16-rc6. > - Fixed some minor comments. > - Thanks Bjorn for the review. > > Changes in v4: > - Regarding the comments to separate ECAM functionality, > I have sent a separate patch and it is decided to implement > it later. The patch is here, > https://lkml.org/lkml/2014/5/18/54 > - Fixed issue with adding configuration bus resource. > - Moved the logic for setting up bus resources to probe() from > pcie_setup(). > - Instead of mapping all the MSI interrupts in the probe, changed > to map only when a MSI is requested. > - Earlier, the implementation of legacy and MSI interrupts init- > is mutually exclusive, now changed to have the legacy interrupts > init always and MSI interrupt init based on CONFIG_PCI_MSI flag. > - Regarding the MSI generic implementation comment, I will plan to > do on top of this driver patch. > - Rebased on 3.16-rc2. > - Fixed other minor comments. > - Thanks Arnd and Bjorn for the review. > > Changes in v3: > - Rebased on v3.15.0-rc1 > - Added support for interrupt-map DT functionality. > - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). > - Modified resource mapping logic as per the series > "PCI: ARM: add support for generic PCI host controller" > - Modified devicetree binding documentation to update with interrupt- > map properties. > - Use devm calls wherever applicable. > - Fixed minor comments from Jason > - Thanks Jason for the review and suggestions. > > Changes in v2: > - Rebased on v3.14.0-rc8 > - Removed IP specific DT properties like include-rc, axibar-num etc., > as suggested by Jason and Bjorn, Thanks > --- > .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ > drivers/pci/host/Kconfig |7 + > drivers/pci/host/Makefile |1 + > drivers/pci/host/pcie-xilinx.c | 978 > > 4 files changed, 1048 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt > create mode 100644 drivers/pci/host/pcie-xilinx.c > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > new file mode 100644 > index 000..3e2c88d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > @@ -0,0 +1,62 @@ > +* Xilinx AXI PCIe Root Port Bridge DT description > + > +Required properties: > +- #address-cells: Address representation for root ports, set to <3> > +- #size-cells: Size representation for root ports, set to <2> > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" > +- reg: Should contain AXI PCIe registers location and length > +- device_type: must be "pci" > +- interrupts: Should contain AXI PCIe interrupt > +- interrupt-map-mask, > + interrupt-map: standard PCI properties to define the mapping of the > + PCI interface to interrupt numbers. > +- ranges: ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + Please refer to the standard PCI bus binding document for a more > + detailed explanation > + > +Optional properties: > +- bus-range: PCI bus numbers covered > + > +Interrupt controller child node > > +Required properties: > +- interrupt-controller: identifies the node as an interrupt controller > +- #address-cells: specifies the number of cells needed to encode an > + address. The value must be 0. > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > + > +NOTE: > +The core provides a single interrupt for both INTx/MSI
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, I fixed the mentioned issues with build-bot in v7. Could you please take this patch? Thanks Srikanth On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala wrote: > This is the driver for Xilinx AXI PCIe Host Bridge Soft IP > > Signed-off-by: Srikanth Thokala > Acked-by: Arnd Bergmann > --- > Changes in v7: > - Removed errors reported from build-bot. The errors are > mainly due to same CONFIG_PCI_XILINX flag being used for > Zynq and Microblaze platforms. So, renamed the driver > config flag name to CONFIG_PCIE_XILINX. > - Also, renamed the driver file to pcie-xilinx.c to be in > sync with CONFIG option. > - Fixed the annotation of xilinx_pcie_scan_bus() function > to remove build-bot warnings. > > Changes in v6: > - Added Ack from Arnd. Thanks Arnd. > - Rebased on 3.16-rc7. > > Changes in v5: > - Removed unnecessary checking of port structure. > - Changed the return type of verify_config from int to bool. > - Renamed following functions, > xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() > xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() > xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() > - Removed link_up bool flag from port structure, as it is not > being used. > - Removed unused constants. > - Rebased on 3.16-rc6. > - Fixed some minor comments. > - Thanks Bjorn for the review. > > Changes in v4: > - Regarding the comments to separate ECAM functionality, > I have sent a separate patch and it is decided to implement > it later. The patch is here, > https://lkml.org/lkml/2014/5/18/54 > - Fixed issue with adding configuration bus resource. > - Moved the logic for setting up bus resources to probe() from > pcie_setup(). > - Instead of mapping all the MSI interrupts in the probe, changed > to map only when a MSI is requested. > - Earlier, the implementation of legacy and MSI interrupts init- > is mutually exclusive, now changed to have the legacy interrupts > init always and MSI interrupt init based on CONFIG_PCI_MSI flag. > - Regarding the MSI generic implementation comment, I will plan to > do on top of this driver patch. > - Rebased on 3.16-rc2. > - Fixed other minor comments. > - Thanks Arnd and Bjorn for the review. > > Changes in v3: > - Rebased on v3.15.0-rc1 > - Added support for interrupt-map DT functionality. > - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). > - Modified resource mapping logic as per the series > "PCI: ARM: add support for generic PCI host controller" > - Modified devicetree binding documentation to update with interrupt- > map properties. > - Use devm calls wherever applicable. > - Fixed minor comments from Jason > - Thanks Jason for the review and suggestions. > > Changes in v2: > - Rebased on v3.14.0-rc8 > - Removed IP specific DT properties like include-rc, axibar-num etc., > as suggested by Jason and Bjorn, Thanks > --- > .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ > drivers/pci/host/Kconfig |7 + > drivers/pci/host/Makefile |1 + > drivers/pci/host/pcie-xilinx.c | 978 > > 4 files changed, 1048 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt > create mode 100644 drivers/pci/host/pcie-xilinx.c > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > new file mode 100644 > index 000..3e2c88d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > @@ -0,0 +1,62 @@ > +* Xilinx AXI PCIe Root Port Bridge DT description > + > +Required properties: > +- #address-cells: Address representation for root ports, set to <3> > +- #size-cells: Size representation for root ports, set to <2> > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" > +- reg: Should contain AXI PCIe registers location and length > +- device_type: must be "pci" > +- interrupts: Should contain AXI PCIe interrupt > +- interrupt-map-mask, > + interrupt-map: standard PCI properties to define the mapping of the > + PCI interface to interrupt numbers. > +- ranges: ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + Please refer to the standard PCI bus binding document for a more > + detailed explanation > + > +Optional properties: > +- bus-range: PCI bus numbers covered > + > +Interrupt controller child node > > +Required properties: > +- interrupt-controller: identifies the node as an interrupt controller > +- #address-cells: specifies the number of cells needed to encode an > + address. The value must be 0. > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > + >
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, I fixed the mentioned issues with build-bot in v7. Could you please take this patch? Thanks Srikanth On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala stho...@xilinx.com wrote: This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala stho...@xilinx.com Acked-by: Arnd Bergmann a...@arndb.de --- Changes in v7: - Removed errors reported from build-bot. The errors are mainly due to same CONFIG_PCI_XILINX flag being used for Zynq and Microblaze platforms. So, renamed the driver config flag name to CONFIG_PCIE_XILINX. - Also, renamed the driver file to pcie-xilinx.c to be in sync with CONFIG option. - Fixed the annotation of xilinx_pcie_scan_bus() function to remove build-bot warnings. Changes in v6: - Added Ack from Arnd. Thanks Arnd. - Rebased on 3.16-rc7. Changes in v5: - Removed unnecessary checking of port structure. - Changed the return type of verify_config from int to bool. - Renamed following functions, xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up() xilinx_pcie_verify_config() - xilinx_pcie_valid_device() xilinx_pcie_get_config_base() - xilinx_pcie_config_base() - Removed link_up bool flag from port structure, as it is not being used. - Removed unused constants. - Rebased on 3.16-rc6. - Fixed some minor comments. - Thanks Bjorn for the review. Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series PCI: ARM: add support for generic PCI host controller - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-xilinx.c | 978 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pcie-xilinx.c diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to 3 +- #size-cells: Size representation for root ports, set to 2 +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain xlnx,axi-pcie-host-1.00.a +- reg: Should contain AXI PCIe registers location and length +- device_type: must be pci +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI messages. So,
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote: This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala stho...@xilinx.com Acked-by: Arnd Bergmann a...@arndb.de Applied to pci/host-xilinx for v3.18, thanks! --- Changes in v7: - Removed errors reported from build-bot. The errors are mainly due to same CONFIG_PCI_XILINX flag being used for Zynq and Microblaze platforms. So, renamed the driver config flag name to CONFIG_PCIE_XILINX. - Also, renamed the driver file to pcie-xilinx.c to be in sync with CONFIG option. - Fixed the annotation of xilinx_pcie_scan_bus() function to remove build-bot warnings. Changes in v6: - Added Ack from Arnd. Thanks Arnd. - Rebased on 3.16-rc7. Changes in v5: - Removed unnecessary checking of port structure. - Changed the return type of verify_config from int to bool. - Renamed following functions, xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up() xilinx_pcie_verify_config() - xilinx_pcie_valid_device() xilinx_pcie_get_config_base() - xilinx_pcie_config_base() - Removed link_up bool flag from port structure, as it is not being used. - Removed unused constants. - Rebased on 3.16-rc6. - Fixed some minor comments. - Thanks Bjorn for the review. Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series PCI: ARM: add support for generic PCI host controller - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-xilinx.c | 978 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pcie-xilinx.c diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to 3 +- #size-cells: Size representation for root ports, set to 2 +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain xlnx,axi-pcie-host-1.00.a +- reg: Should contain AXI PCIe registers location and length +- device_type: must be pci +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI messages. So, +created a interrupt controller node to support 'interrupt-map' DT +functionality.
[PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So, renamed the driver
config flag name to CONFIG_PCIE_XILINX.
- Also, renamed the driver file to pcie-xilinx.c to be in
sync with CONFIG option.
- Fixed the annotation of xilinx_pcie_scan_bus() function
to remove build-bot warnings.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.16-rc7.
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
"PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pcie-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = <3>;
+
[PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So, renamed the driver
config flag name to CONFIG_PCIE_XILINX.
- Also, renamed the driver file to pcie-xilinx.c to be in
sync with CONFIG option.
- Fixed the annotation of xilinx_pcie_scan_bus() function
to remove build-bot warnings.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.16-rc7.
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pcie-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells =
