[PATCH v7 02/42] clk: davinci: New driver for davinci PLL clocks

2018-02-19 Thread David Lechner 
This adds a new driver for mach-davinci PLL clocks. This is porting the
code from arch/arm/mach-davinci/clock.c to the common clock framework.
Additionally, it adds device tree support for these clocks.

The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent
compile errors until the clock code in arch/arm/mach-davinci is removed.

Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the register
layouts are a bit different, which would add even more if/else mess
to the keystone clocks. And the keystone PLL driver doesn't support
setting clock rates.

Signed-off-by: David Lechner 
---

v7 changes:
- convert to platform device driver
- rename PLL_HAS_OSCIN to PLL_HAS_CLKMODE
- add comments to clarify which clock domain "oscin" is

v6 changes:
- Added R: Sekhar Nori  to MAINTAINERS
- Split main PLL clock into oscdiv, prediv, pllout, postdiv and pllen clocks
- Added min/max rate checking for pllout in set_rate
- Added min/max PLLM value checking for pllout in set_rate
- Fixed sysclk set_rate (checking GOSTAT and setting GOSET)
- Added *_clk_info structs for passing controller-specific info
- Added quirks for optional PREDIV and POSTDIV registers
- Added quirk for DM355 broken PREDIV register
- Added quirk for DM365 2x PLLM register
- Handle unlocking PLL registers via CFGCHIP
- Use pr_fmt macro


 MAINTAINERS  |   7 +
 drivers/clk/Makefile |   1 +
 drivers/clk/davinci/Makefile |   5 +
 drivers/clk/davinci/pll.c| 864 +++
 drivers/clk/davinci/pll.h| 120 ++
 5 files changed, 997 insertions(+)
 create mode 100644 drivers/clk/davinci/Makefile
 create mode 100644 drivers/clk/davinci/pll.c
 create mode 100644 drivers/clk/davinci/pll.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 9a7f76e..7d5c129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13794,6 +13794,13 @@ F: arch/arm/mach-davinci/
 F: drivers/i2c/busses/i2c-davinci.c
 F: arch/arm/boot/dts/da850*
 
+TI DAVINCI SERIES CLOCK DRIVER
+M: David Lechner 
+R: Sekhar Nori 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/ti/davinci/
+F: drivers/clk/davinci/
+
 TI DAVINCI SERIES GPIO DRIVER
 M: Keerthy 
 L: linux-g...@vger.kernel.org
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71ec41e..07ac0fdb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/
 obj-$(CONFIG_ARC_PLAT_AXS10X)  += axs10x/
 obj-y  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
+obj-$(CONFIG_ARCH_DAVINCI) += davinci/
 obj-$(CONFIG_H8300)+= h8300/
 obj-$(CONFIG_ARCH_HISI)+= hisilicon/
 obj-y  += imgtec/
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
new file mode 100644
index 000..d9673bd
--- /dev/null
+++ b/drivers/clk/davinci/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-y += pll.o
+endif
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
new file mode 100644
index 000..e4f3e5f
--- /dev/null
+++ b/drivers/clk/davinci/pll.c
@@ -0,0 +1,864 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock driver for TI Davinci SoCs
+ *
+ * Copyright (C) 2018 David Lechner 
+ *
+ * Based on arch/arm/mach-davinci/clock.c
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pll.h"
+
+#define MAX_NAME_SIZE  20
+#define OSCIN_CLK_NAME "oscin"
+
+#define REVID  0x000
+#define PLLCTL 0x100
+#define OCSEL  0x104
+#define PLLSECCTL  0x108
+#define PLLM   0x110
+#define PREDIV 0x114
+#define PLLDIV10x118
+#define PLLDIV20x11c
+#define PLLDIV30x120
+#define OSCDIV 0x124
+#define POSTDIV0x128
+#define BPDIV  0x12c
+#define PLLCMD 0x138
+#define PLLSTAT0x13c
+#define ALNCTL 0x140
+#define DCHANGE0x144
+#define CKEN   0x148
+#define CKSTAT 0x14c
+#define SYSTAT 0x150
+#define PLLDIV40x160
+#define PLLDIV50x164
+#define PLLDIV60x168
+#define PLLDIV70x16c
+#define PLLDIV80x170
+#define PLLDIV90x174
+
+#define PLLCTL_PLLEN   BIT(0)
+#define PLLCTL_PLLPWRDNBIT(1)

[PATCH v7 02/42] clk: davinci: New driver for davinci PLL clocks

2018-02-19 Thread David Lechner 
This adds a new driver for mach-davinci PLL clocks. This is porting the
code from arch/arm/mach-davinci/clock.c to the common clock framework.
Additionally, it adds device tree support for these clocks.

The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent
compile errors until the clock code in arch/arm/mach-davinci is removed.

Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the register
layouts are a bit different, which would add even more if/else mess
to the keystone clocks. And the keystone PLL driver doesn't support
setting clock rates.

Signed-off-by: David Lechner 
---

v7 changes:
- convert to platform device driver
- rename PLL_HAS_OSCIN to PLL_HAS_CLKMODE
- add comments to clarify which clock domain "oscin" is

v6 changes:
- Added R: Sekhar Nori  to MAINTAINERS
- Split main PLL clock into oscdiv, prediv, pllout, postdiv and pllen clocks
- Added min/max rate checking for pllout in set_rate
- Added min/max PLLM value checking for pllout in set_rate
- Fixed sysclk set_rate (checking GOSTAT and setting GOSET)
- Added *_clk_info structs for passing controller-specific info
- Added quirks for optional PREDIV and POSTDIV registers
- Added quirk for DM355 broken PREDIV register
- Added quirk for DM365 2x PLLM register
- Handle unlocking PLL registers via CFGCHIP
- Use pr_fmt macro


 MAINTAINERS  |   7 +
 drivers/clk/Makefile |   1 +
 drivers/clk/davinci/Makefile |   5 +
 drivers/clk/davinci/pll.c| 864 +++
 drivers/clk/davinci/pll.h| 120 ++
 5 files changed, 997 insertions(+)
 create mode 100644 drivers/clk/davinci/Makefile
 create mode 100644 drivers/clk/davinci/pll.c
 create mode 100644 drivers/clk/davinci/pll.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 9a7f76e..7d5c129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13794,6 +13794,13 @@ F: arch/arm/mach-davinci/
 F: drivers/i2c/busses/i2c-davinci.c
 F: arch/arm/boot/dts/da850*
 
+TI DAVINCI SERIES CLOCK DRIVER
+M: David Lechner 
+R: Sekhar Nori 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/ti/davinci/
+F: drivers/clk/davinci/
+
 TI DAVINCI SERIES GPIO DRIVER
 M: Keerthy 
 L: linux-g...@vger.kernel.org
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71ec41e..07ac0fdb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/
 obj-$(CONFIG_ARC_PLAT_AXS10X)  += axs10x/
 obj-y  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
+obj-$(CONFIG_ARCH_DAVINCI) += davinci/
 obj-$(CONFIG_H8300)+= h8300/
 obj-$(CONFIG_ARCH_HISI)+= hisilicon/
 obj-y  += imgtec/
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
new file mode 100644
index 000..d9673bd
--- /dev/null
+++ b/drivers/clk/davinci/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-y += pll.o
+endif
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
new file mode 100644
index 000..e4f3e5f
--- /dev/null
+++ b/drivers/clk/davinci/pll.c
@@ -0,0 +1,864 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock driver for TI Davinci SoCs
+ *
+ * Copyright (C) 2018 David Lechner 
+ *
+ * Based on arch/arm/mach-davinci/clock.c
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pll.h"
+
+#define MAX_NAME_SIZE  20
+#define OSCIN_CLK_NAME "oscin"
+
+#define REVID  0x000
+#define PLLCTL 0x100
+#define OCSEL  0x104
+#define PLLSECCTL  0x108
+#define PLLM   0x110
+#define PREDIV 0x114
+#define PLLDIV10x118
+#define PLLDIV20x11c
+#define PLLDIV30x120
+#define OSCDIV 0x124
+#define POSTDIV0x128
+#define BPDIV  0x12c
+#define PLLCMD 0x138
+#define PLLSTAT0x13c
+#define ALNCTL 0x140
+#define DCHANGE0x144
+#define CKEN   0x148
+#define CKSTAT 0x14c
+#define SYSTAT 0x150
+#define PLLDIV40x160
+#define PLLDIV50x164
+#define PLLDIV60x168
+#define PLLDIV70x16c
+#define PLLDIV80x170
+#define PLLDIV90x174
+
+#define PLLCTL_PLLEN   BIT(0)
+#define PLLCTL_PLLPWRDNBIT(1)
+#define PLLCTL_PLLRST  BIT(3)
+#define PLLCTL_PLLDIS  BIT(4)
+#define PLLCTL_PLLENSRC