Re: [PATCH v7 04/11] clk: actions: Add gate clock support

2018-04-06 Thread Stephen Boyd 
Quoting Manivannan Sadhasivam (2018-03-26 10:38:58)
> Add support for Actions Semi gate clock together with helper
> functions to be used in composite clock.
> 
> Signed-off-by: Manivannan Sadhasivam 
> ---

Applied to clk-next

Re: [PATCH v7 04/11] clk: actions: Add gate clock support

2018-04-06 Thread Stephen Boyd 
Quoting Manivannan Sadhasivam (2018-03-26 10:38:58)
> Add support for Actions Semi gate clock together with helper
> functions to be used in composite clock.
> 
> Signed-off-by: Manivannan Sadhasivam 
> ---

Applied to clk-next

[PATCH v7 04/11] clk: actions: Add gate clock support

2018-03-26 Thread Manivannan Sadhasivam 
Add support for Actions Semi gate clock together with helper
functions to be used in composite clock.

Signed-off-by: Manivannan Sadhasivam 
---
 drivers/clk/actions/Makefile   |  1 +
 drivers/clk/actions/owl-gate.c | 77 ++
 drivers/clk/actions/owl-gate.h | 73 +++
 3 files changed, 151 insertions(+)
 create mode 100644 drivers/clk/actions/owl-gate.c
 create mode 100644 drivers/clk/actions/owl-gate.h

diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
index 64a50fc2d335..1f0917872c9d 100644
--- a/drivers/clk/actions/Makefile
+++ b/drivers/clk/actions/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_CLK_ACTIONS)  += clk-owl.o
 
 clk-owl-y  += owl-common.o
+clk-owl-y  += owl-gate.o
diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c
new file mode 100644
index ..f11500ba46a7
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu 
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam 
+
+#include 
+#include 
+
+#include "owl-gate.h"
+
+void owl_gate_set(const struct owl_clk_common *common,
+const struct owl_gate_hw *gate_hw, bool enable)
+{
+   int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+   u32 reg;
+
+   set ^= enable;
+
+   regmap_read(common->regmap, gate_hw->reg, );
+
+   if (set)
+   reg |= BIT(gate_hw->bit_idx);
+   else
+   reg &= ~BIT(gate_hw->bit_idx);
+
+   regmap_write(common->regmap, gate_hw->reg, reg);
+}
+
+static void owl_gate_disable(struct clk_hw *hw)
+{
+   struct owl_gate *gate = hw_to_owl_gate(hw);
+   struct owl_clk_common *common = >common;
+
+   owl_gate_set(common, >gate_hw, false);
+}
+
+static int owl_gate_enable(struct clk_hw *hw)
+{
+   struct owl_gate *gate = hw_to_owl_gate(hw);
+   struct owl_clk_common *common = >common;
+
+   owl_gate_set(common, >gate_hw, true);
+
+   return 0;
+}
+
+int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
+  const struct owl_gate_hw *gate_hw)
+{
+   u32 reg;
+
+   regmap_read(common->regmap, gate_hw->reg, );
+
+   if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
+   reg ^= BIT(gate_hw->bit_idx);
+
+   return !!(reg & BIT(gate_hw->bit_idx));
+}
+
+static int owl_gate_is_enabled(struct clk_hw *hw)
+{
+   struct owl_gate *gate = hw_to_owl_gate(hw);
+   struct owl_clk_common *common = >common;
+
+   return owl_gate_clk_is_enabled(common, >gate_hw);
+}
+
+const struct clk_ops owl_gate_ops = {
+   .disable= owl_gate_disable,
+   .enable = owl_gate_enable,
+   .is_enabled = owl_gate_is_enabled,
+};
diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h
new file mode 100644
index ..c2d61ceebce2
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu 
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam 
+
+#ifndef _OWL_GATE_H_
+#define _OWL_GATE_H_
+
+#include "owl-common.h"
+
+struct owl_gate_hw {
+   u32 reg;
+   u8  bit_idx;
+   u8  gate_flags;
+};
+
+struct owl_gate {
+   struct owl_gate_hw  gate_hw;
+   struct owl_clk_common   common;
+};
+
+#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags)   \
+   {   \
+   .reg= _reg, \
+   .bit_idx= _bit_idx, \
+   .gate_flags = _gate_flags,  \
+   }
+
+#define OWL_GATE(_struct, _name, _parent, _reg,
\
+   _bit_idx, _gate_flags, _flags)  \
+   struct owl_gate _struct = { \
+   .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags),\
+   .common = { \
+   .regmap = NULL, \
+   .hw.init= CLK_HW_INIT(_name,\
+ _parent,  \
+ _gate_ops,\
+ _flags),  \
+   }   \
+   }

[PATCH v7 04/11] clk: actions: Add gate clock support

2018-03-26 Thread Manivannan Sadhasivam 
Add support for Actions Semi gate clock together with helper
functions to be used in composite clock.

Signed-off-by: Manivannan Sadhasivam 
---
 drivers/clk/actions/Makefile   |  1 +
 drivers/clk/actions/owl-gate.c | 77 ++
 drivers/clk/actions/owl-gate.h | 73 +++
 3 files changed, 151 insertions(+)
 create mode 100644 drivers/clk/actions/owl-gate.c
 create mode 100644 drivers/clk/actions/owl-gate.h

diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
index 64a50fc2d335..1f0917872c9d 100644
--- a/drivers/clk/actions/Makefile
+++ b/drivers/clk/actions/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_CLK_ACTIONS)  += clk-owl.o
 
 clk-owl-y  += owl-common.o
+clk-owl-y  += owl-gate.o
diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c
new file mode 100644
index ..f11500ba46a7
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu 
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam 
+
+#include 
+#include 
+
+#include "owl-gate.h"
+
+void owl_gate_set(const struct owl_clk_common *common,
+const struct owl_gate_hw *gate_hw, bool enable)
+{
+   int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+   u32 reg;
+
+   set ^= enable;
+
+   regmap_read(common->regmap, gate_hw->reg, );
+
+   if (set)
+   reg |= BIT(gate_hw->bit_idx);
+   else
+   reg &= ~BIT(gate_hw->bit_idx);
+
+   regmap_write(common->regmap, gate_hw->reg, reg);
+}
+
+static void owl_gate_disable(struct clk_hw *hw)
+{
+   struct owl_gate *gate = hw_to_owl_gate(hw);
+   struct owl_clk_common *common = >common;
+
+   owl_gate_set(common, >gate_hw, false);
+}
+
+static int owl_gate_enable(struct clk_hw *hw)
+{
+   struct owl_gate *gate = hw_to_owl_gate(hw);
+   struct owl_clk_common *common = >common;
+
+   owl_gate_set(common, >gate_hw, true);
+
+   return 0;
+}
+
+int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
+  const struct owl_gate_hw *gate_hw)
+{
+   u32 reg;
+
+   regmap_read(common->regmap, gate_hw->reg, );
+
+   if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
+   reg ^= BIT(gate_hw->bit_idx);
+
+   return !!(reg & BIT(gate_hw->bit_idx));
+}
+
+static int owl_gate_is_enabled(struct clk_hw *hw)
+{
+   struct owl_gate *gate = hw_to_owl_gate(hw);
+   struct owl_clk_common *common = >common;
+
+   return owl_gate_clk_is_enabled(common, >gate_hw);
+}
+
+const struct clk_ops owl_gate_ops = {
+   .disable= owl_gate_disable,
+   .enable = owl_gate_enable,
+   .is_enabled = owl_gate_is_enabled,
+};
diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h
new file mode 100644
index ..c2d61ceebce2
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu 
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam 
+
+#ifndef _OWL_GATE_H_
+#define _OWL_GATE_H_
+
+#include "owl-common.h"
+
+struct owl_gate_hw {
+   u32 reg;
+   u8  bit_idx;
+   u8  gate_flags;
+};
+
+struct owl_gate {
+   struct owl_gate_hw  gate_hw;
+   struct owl_clk_common   common;
+};
+
+#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags)   \
+   {   \
+   .reg= _reg, \
+   .bit_idx= _bit_idx, \
+   .gate_flags = _gate_flags,  \
+   }
+
+#define OWL_GATE(_struct, _name, _parent, _reg,
\
+   _bit_idx, _gate_flags, _flags)  \
+   struct owl_gate _struct = { \
+   .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags),\
+   .common = { \
+   .regmap = NULL, \
+   .hw.init= CLK_HW_INIT(_name,\
+ _parent,  \
+ _gate_ops,\
+ _flags),  \
+   }   \
+   }   \
+
+#define OWL_GATE_NO_PARENT(_struct, _name, _reg,   \
+   _bit_idx, _gate_flags,